Hi Ryan


So I just finished a ROACH2 build, and everything from "copy base package" through bitgen took almost 2 hours. It looks like this is because I have 48 "shared memories", plus about another 20 "snapshots". The tools seem to be synthesizing each of these separately.

I would expect that many designs have several yellow blocks which are instantiated multiple times with identical parameters. I don't have a strong background in the CASPER toolflow, but does anyone know if there's a way for us to cache synthesis products of identical yellow blocks?

As far as I know Dave (M) uses black-boxing for doing this with some parts of the DSP design (i.e not necessarily yellow blocks). He also implemented some logic recently to cache and reuse Shared BRAM coregen products (as these also take a while to generate).

I have mentioned this idea before to Dave but I think that it would be possible to take this idea a lot further. The toolflow could automate this quite easily. Basically, at compile time do the following;
1. For every 'large' CASPER DSP/yellow block
a. check that we don't already have the synthesis products for this block in our database, if so skip to 2. b. make a new design and copy it across, joining input ports to Getway Ins and outputs to Gateway outs
    c. synthesise the resultant design with System Generator
2. Create a copy of the original full design and replace each 'large' block with a black box
3. Synthesise the modified full design
4. Have the toolflow copy the required output products from the small component block compiles into the appropriate place and join everything up (much like we already do with the yellow blocks) 5. On subsequent compiles, check the 'large' blocks for changes (hash the parameter inputs and maybe some other things) and only re-synthesise those blocks that have changed. 6. Logic could also be added to build up a local database of compiled blocks that could be queried when a compile of a design occurs

It would be a reasonable amount of work to implement, but would save a lot of time for people who compile the same design often.

Regards
Andrew


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