Hi, Andrew, On Jul 23, 2013, at 7:54 AM, Andrew Martens wrote:
> The only way that the script could generate logic that would result in > correct data would be correct if; > 1. The Relational block could get a latency of 1 when no latency was > specified i.e default operation has latency of 1 in that toolflow version. You're right! That's exactly the problem. In System Generator version 13.3.4175 (at least in the copy of it that I use), the Relational block has a default latency of 1. In System Generator version 14.2.4415 (at least the copy of it that I use) the Relational block has a default latency of 0. I looks like the mirror_spectrum_init function is one of a few places in the casper libraries where a Relation block is placed without explicitly setting its latency. This will result in different latencies (and therefore overall behavior) for such blocks depending on which version of the System Generator is used. I only found two other places where this happens: 1) address_gen_vacc_v2_mask,m - This will affect the dram_vacc block. 2) delay_wideband_prog_init.m - This affects the delay_wideband_prog block, but only when it is configured to use Single Port BRAM. Unfortunately, I think that block might have other issues because I could not get a test model to function as expected for either System Generator version. It looks like your updates to the mirror_spectrum_init script still leave the latency of the Relational block unspecified. It would be great if you could add an explicit latency value to that block. That would make your update compatible with both older and newer versions of System Generator. I just compared the latencies of all the Xilinx blocks between 13.3.4175 and 14.2.4415. Only the Relational block had a change in latency so no other problems of this nature are likely to be lurking out there. Thanks, Dave
