Hi Rurik and casperians, I run into the problem where to change the bandwidth to LOW. On xilinx webpage, it's told to configure it with fpga_editor. However, fpga_editor asks for mapped .ncd files, and neither matlab nor planahead could produce the .ncd file because of the DRC runned at beginning of mapping. Could some one give me some idea of how and from where to make this change?
Has anyone tested that setting bandwidth to LOW with fpga clocked at 312.5MHz (adc5g 2500MHz) would affect the performance? Thanks! Weiwei
