Hi Dan Thanks for your input.
For 800 MHz BW, I am looking for 2048 spectral channels. If that is a tall order, we could settle for 1024. I am hoping to double the number of channels for halving the BW. For eg. BW NumChannels 800 2048 400 4096 200 8192 I see why you are suggesting the ASIAA dual adc card for the 800 MHz mode. But I would prefer if we could use the same ADC for all modes. If I were to use the ASIAA ADC sampling at 1.6 GHz (FPGA clock ~ 200 MHz), and use all 8 parallel streams of the ADC for PFB and FFT then I satisfy that mode. For the 400 MHz mode, if I leave the sampling clock at 1.6 GHz, but terminate 4 outputs of the 8 parallel streams from the ADC, am I not effectively sampling at 800 MHz? Can a similar argument not be applied for 400 MHz sampling? What are the downsides to taking this approach? Am I missing something obvious? Cheers, Gopal On Thu, Mar 20, 2014 at 3:43 PM, Dan Werthimer <[email protected]>wrote: > > hi gopal, > > how many spectral channels do you need? > > for 800 MHz bandwidth, you can use a pair of asiaa dual adc's at 2Gsps, > and get four signal inputs per roach2, and clock the fgpa at 250 MHz. . > > for 400 MHz bandwidth, i suggest you use a pair of adc16 boards > in quad input mode (sample at 960 Msps, four inputs per board), so > you can get 8 signal inputs per roach2. fpga clock of 240 MHz. > we might have a design for this you can use if you'd like. > > for 200 MHz bandwidth, i suggest you use a pair of adc16 boards > in octal input mode (sample at 480 Msps, eight inputs per board), so > you can get 16 signal inputs per roach2. fpga clock of 240 MHz. > > best wishes, > > dan > > > > > On Thu, Mar 20, 2014 at 10:08 AM, Gopal Narayanan > <[email protected]>wrote: > >> Hello Casperites >> >> I'm looking for advice. We are at the point of launching into a wideband >> spectrometer project for building ROACH-2 based spectrometers to handle 32 >> independent front-end inputs. This is a conventional spectrometer (no >> cross-correlations needed). Our maximum bandwidth needed is 800 MHz. We are >> also interested in modes of bandwidth 200 and 400 MHz. I should note that >> legacy IF processors with band-limiting filters for the above BWs already >> exist, and we are building our spectrometer to these bandwidths. >> >> I am debating between the KatADC board and the wideband ASIAA 5GSPS ADC >> based boards. I ran some preliminary Simulink designs with the KatADC >> boards, and I run into timing issues when I use ADC sampling rate > 1200 >> MHz. For 1.5 GSPS sampling, the FPGA clock gets up to 375 MHz with the >> KatADC, so perhaps this is the issue. I would like to squeeze 4 pixels into >> one ROACH-2 if possible. Has anyone run the KatADC close to its maximum >> sampling rate with the ROACH-2s? Are plan-ahead and other more advanced >> techniques needed for this? >> >> Alternatively, we could use the ASIAA ADC board, which has a divided-by-8 >> for the FPGA clock from the ADC sample rate. Keeping FPGA clock rates at >> nominal values might be easier with the ASIAA board, especially when we are >> only interested in relatively low sample clocks to 1.6 GHz. We are >> considering the 8-bit DMUX 1:1 version of the ASIAA board. >> >> Any pointers/advice/suggestions in choosing an appropriate ADC board is >> appreciated! >> >> Thanks >> Gopal >> >> >> -- >> Gopal Narayanan Ph #: (413) 545 0925 >> Department of Astronomy e-mail: [email protected] >> University of Massachusetts Amherst MA 01003 >> >> > -- Gopal Narayanan Ph #: (413) 545 0925 Department of Astronomy e-mail: [email protected] University of Massachusetts Amherst MA 01003
