Hey Ryan, This sounds great. I've just got a 312mhz design for a project in Cambridge to meet timing (broadly similar to what you're describing, but 10 single pol antennas and only 4k channels over 5ghz bw). Whilst I don't have any particular requests, I would be very interested in hearing about how you end up reaching 375mhz. (What granularity you place pblocks/cunning code optimisations/etc). I found my experience to be educational, if a bit frustrating, and I'd be interested to know the gritty details used by others (equally, if anyone cares, I'm very happy to talk about my tactics). I certainly found that a vague high-level placement of pblocks with the standard mlibdevel libraries didn't work as well as I was hoping.
Cheers, Jack On 29 Oct 2014 22:26, "Ryan Monroe" <ryan.m.mon...@gmail.com> wrote: > Hey guys, > > The CASPER community has been a great help to me in the past few years. > People have asked for my libraries and due to JPL policy, I've always had > to turn them away. Thanks to help from Bob Jarnot, Jonathon Kocz and > others, I'm now free to open-source some of my designs/libraries. > > For my PhD, I'm designing a 10gsps correlator. I'd really like for this > to be an extremely versatile design, useful for radioastronomy and > earth-observing-science, good for all broadband, low-N applications. *If > there are any special features you'd like to see in this design, beyond > what is listed below, tell me now!* I'm willing to add it, but I have to > know before everything is finished up. > > Stats are: > > (note: N bits complex means N bits for each of real and imag) > > Mode "A": > Dual-polarization full-stokes, > 2.5 GHz per pol > 8192-channel (per pol) > 8-tap hamming PFB > > Mode "B": > I/Q separating spectrometer > 5 GHz total bandwidth > 16384 channels across entire band > 8-tap hamming PFB > > Features common to both: > Time-domain delay tracking (sample resolution; 48k-sample range) > Frequency domain delay tracking (linear interpolation, set two registers > to update) > Bandpass calibration (applied before I/Q separation): unique 16 bit > complex gain applied to each signal= sideband rejection much greater than > ADC SNR > 10GBE full-duty cycle dump rate (4bits complex per sample) > 1GBE accumulation dumps. accumulations supported [10ms -> 100s for > spectrometer only]; [10ms -> 1s for correlator] > Everything is synchronized off 1pps and the end of an FFT. > Triggered accumulations via GPIO, software register or 1pps (accumulations > can be one-off or continuous) > > In addition, the design will include a X-engine correlator (2 antennas, > each 2-pol). The corner turn is performed simply by wiring 10gbe cables. > The design can be used as a spectrometer though. The design requires an > FPGA clock rate of 312.5 MHz, but I'm going to try for 375 MHz so that we > can overclock if we want to (or if we get better ADCs later) > > I really want to make this a versatile, general purpose, broadband, > spectrometer/low-N correlator. > > Features I could add if people want: > > DDR circular buffer (4bits of each adc sample, 1.6s of buffer@16 GB of > ram) [requested by tom kuiper/majin walid] > Larger x-engine (4 dual-pol antennas for charity, I could do 8 but it > would be lots of work so we'll have to talk in that case) > ADC core matching (if my old firmware for this still works!) > *your feature request here????* > > > I look forward to your input! As a friendly reminder, my track record for > designing FPGA firmware is extremely good, but this might not all pan out > as expected. I'm making no promises quite yet. > > Timeline is currently to have simulated firmware which meets timing at > 312.5 MHz (equals 5 GHz total bandwidth) by dec1. Fingers crossed! > > > --Ryan >
