Hi Ryan, That does look cool! You don’t mention which ADC you plan to use. Is it this one?
https://casper.berkeley.edu/wiki/ADC1x5000-8 Just to mention in case it proves useful that our group at Submillimeter Array (SMA) and Event Horizon Telescope (EHT) has been working on a correlator / phased array system with what appear to be rather similar features (low N, wideband, high spectral resolution 32 k PFB etc) using the above ADC (DMUX 1:1 version) and ROACH2. We view it as dual 5 Gsps, but I suppose one might interpret that as 10Gsps. There are specs, a little outdated, here: https://www.cfa.harvard.edu/twiki5/view/SMAwideband/DigitalBackEnd This page includes a link to our open source githup repo with all model files. We have done a fair amount of work on ADC core calibration too, also on the wiki, poke around. The key results were recently published here: http://www.worldscientific.com/doi/pdfplus/10.1142/S2251171714500019?src=recsys There is also a recent publication by Jiang et al on the ADC in PASP: Vol. 126, No. 942 (August 2014), pp. 761-768 At this point have the logic for this correlator reduced to a fully working V6 bit code with all features except the phased array (design in progress). In fact, we are routinely taking observational data at SMA, and plan to field it for science in mid-November. However it is not yet running at our eventual design speed goal of 286 MHz, corresponding to 4.6 Gsps at the ADC—a little more modest than your 5 Gsps. Our experience attempting to meet 286 MHz with this complex of a design has been sobering so far, though we have not given up. If you really are able to get a comparable design running at 375 MHz with -1 speed grade parts, honestly you’d deserve an attaboy or two. And we’d gladly learn from how you got there, so please keep us in the loop. By the way, assuming you are using the ADC referenced with the architecture you describe I’d suggest it is appropriate to cite all above referenced and other relevant prior work in your PhD. Best of luck with it. Jonathan and SMA / EHT team > On Oct 29, 2014, at 6:25 PM, Ryan Monroe <ryan.m.mon...@gmail.com> wrote: > > Hey guys, > > The CASPER community has been a great help to me in the past few years. > People have asked for my libraries and due to JPL policy, I've always had to > turn them away. Thanks to help from Bob Jarnot, Jonathon Kocz and others, > I'm now free to open-source some of my designs/libraries. > > For my PhD, I'm designing a 10gsps correlator. I'd really like for this to > be an extremely versatile design, useful for radioastronomy and > earth-observing-science, good for all broadband, low-N applications. If > there are any special features you'd like to see in this design, beyond what > is listed below, tell me now! I'm willing to add it, but I have to know > before everything is finished up. > > Stats are: > > (note: N bits complex means N bits for each of real and imag) > > Mode "A": > Dual-polarization full-stokes, > 2.5 GHz per pol > 8192-channel (per pol) > 8-tap hamming PFB > > Mode "B": > I/Q separating spectrometer > 5 GHz total bandwidth > 16384 channels across entire band > 8-tap hamming PFB > > Features common to both: > Time-domain delay tracking (sample resolution; 48k-sample range) > Frequency domain delay tracking (linear interpolation, set two registers to > update) > Bandpass calibration (applied before I/Q separation): unique 16 bit complex > gain applied to each signal= sideband rejection much greater than ADC SNR > 10GBE full-duty cycle dump rate (4bits complex per sample) > 1GBE accumulation dumps. accumulations supported [10ms -> 100s for > spectrometer only]; [10ms -> 1s for correlator] > Everything is synchronized off 1pps and the end of an FFT. > Triggered accumulations via GPIO, software register or 1pps (accumulations > can be one-off or continuous) > > In addition, the design will include a X-engine correlator (2 antennas, each > 2-pol). The corner turn is performed simply by wiring 10gbe cables. The > design can be used as a spectrometer though. The design requires an FPGA > clock rate of 312.5 MHz, but I'm going to try for 375 MHz so that we can > overclock if we want to (or if we get better ADCs later) > > I really want to make this a versatile, general purpose, broadband, > spectrometer/low-N correlator. > > Features I could add if people want: > > DDR circular buffer (4bits of each adc sample, 1.6s of buffer@16 GB of ram) > [requested by tom kuiper/majin walid] > Larger x-engine (4 dual-pol antennas for charity, I could do 8 but it would > be lots of work so we'll have to talk in that case) > ADC core matching (if my old firmware for this still works!) > your feature request here???? > > > I look forward to your input! As a friendly reminder, my track record for > designing FPGA firmware is extremely good, but this might not all pan out as > expected. I'm making no promises quite yet. > > Timeline is currently to have simulated firmware which meets timing at 312.5 > MHz (equals 5 GHz total bandwidth) by dec1. Fingers crossed! > > > --Ryan
