Hi Ryan, I could get rid of those errors but the tool had hard time in placing with huge setup timing errors. How much utilization is good to set on p-blocks ?
Currently, I had 60-70% for different components. Cheers, Amit On 05-Nov-15 9:46 AM, Ryan Monroe wrote: > Hi Amit, > > FYI, I am CC'ing the CASPER list on all of these emails, so that they > can be searchable for people in the future. > > The placements I gave you were for my personal design, and may not work > for yours. When choosing pblock size, be sure to look at the pblock > utilization in planahead. odds are that you had either > 1. a pblock which was outright too small for the components placed > within (tools error out almost instantly) > 2. multiple overlapping pblocks, in such a way that it's impossible to > satisfy both constraints simultaneously (tools error out after much > longer). pblock statistics don't help with this one, but you can bash > it out by hand with more difficulty. > > look at the error from line 327-561 on your report. this indicates the > constraints which caused the issue, as well as some of the components > involved. that's a good place to start! > > --Ryan > > On 11/05/2015 12:20 AM, aban...@mpifr-bonn.mpg.de wrote: >> Hi Ryan, >> >> I tried to place the 10gbe pblocks as you suggested. Unfortunately, >> the tool was unable to place all components. The pblock statistics >> were more than enough. Do you know how to avoid this problem ? The >> tool took long time to give out errors (~11 hrs). >> >> I have enclosed the map report. >> >> Regards, >> Amit >> >> On 04.11.2015 09:37, Ryan Monroe wrote: >>> np! the 10gbe core wasn't really intended to run at fast clock >>> rates. Be sure to constrain it to the east-ish side of the chip, this >>> is almost either a >>> 1. device utilization issue (you are trying to do too much stuff on >>> the chip), or >>> 2. placement issue (probably this)-- the tools are terrible at >>> placing things in the right spots >>> >>> Send me any questions you have, but I'm pretty busy and reserve the >>> right to be bad about answering ;-) >>> >>> --Ryan >>> >>> >>> >>> On 11/04/2015 12:32 AM, Amit Bansod wrote: >>>> Hi Ryan, >>>> >>>> Thanks a lot! I will give this a try! >>>> >>>> Cheers, >>>> Amit >>>> >>>> On 04-Nov-15 9:31 AM, Ryan Monroe wrote: >>>>> Dear Amit, >>>>> >>>>> Please consider my memo 50 on the CASPER list: "Performance >>>>> optimization >>>>> for Virtex 6 CASPER designs" [1] >>>>> >>>>> As it turns out, I have a design open right now, which must close 8 >>>>> 10gbe cores at 312.5 mhz. Attached is an image of where I placed my >>>>> tge_tx_inst and tge_rx_inst pblocks, which I hope will be helpful for >>>>> you. Wish I had time to do more for you, but such is life :-/ >>>>> >>>>> Cheers! >>>>> >>>>> --Ryan Monroe >>>>> >>>>> [1] https://casper.berkeley.edu/wiki/Memos >>>>> >>>>> On 11/04/2015 12:17 AM, aban...@mpifr-bonn.mpg.de wrote: >>>>>> Dear All, >>>>>> >>>>>> I am getting following timing errors on 10GbE yellow blocks which >>>>>> I am >>>>>> finding it hard to get rid off. I am running my design at 200 MHz. I >>>>>> have given the device utilization summary if it is useful. I have >>>>>> also >>>>>> enclosed the files. >>>>>> >>>>>> Best Regards, >>>>>> Amit >>>>>> >>>>>> Timing Errors: >>>>>> Timing constraint: PERIOD analysis for net >>>>>> "d_codd_64ch_2_P0_ADC_asiaa_adc5g/d_codd_64ch_2_P0_ADC_asiaa_adc5g/ >>>>>> mmcm_clkout1" derived from PERIOD analysis for net >>>>>> "d_codd_64ch_2_P0_ADC_asiaa_adc5g/d_codd_64ch_2_P0_ADC_asiaa_adc5g/ >>>>>> adc_clk_div" derived from NET >>>>>> >>>>>> >>>>>> "d_codd_64ch_2_P0_ADC_asiaa_adc5g/d_codd_64ch_2_P0_ADC_asiaa_adc5g/adc_clk" >>>>>> >>>>>> >>>>>> PERIOD = 2.5 ns HIGH 50%; multiplied by 2.00 to 5 nS and duty >>>>>> cycle >>>>>> corrected to HIGH 2.500 nS >>>>>> For more information, see Period Analysis in the Timing Closure >>>>>> User >>>>>> Guide (UG612). >>>>>> >>>>>> 1594959 paths analyzed, 343705 endpoints analyzed, 63 failing >>>>>> endpoints >>>>>> 63 timing errors detected. (63 setup errors, 0 hold errors, 0 >>>>>> component switching limit errors) >>>>>> Minimum period is 5.727ns. >>>>>> >>>>>> >>>>>> -------------------------------------------------------------------------------- >>>>>> >>>>>> >>>>>> Slack: -0.727ns (requirement - (data path - clock >>>>>> path skew + uncertainty)) >>>>>> Source: >>>>>> >>>>>> d_codd_64ch_2_10G_10GBE2_gbe00/d_codd_64ch_2_10G_10GBE2_gbe00/tge_tx_inst/app_tx_validR >>>>>> >>>>>> (FF) >>>>>> Destination: >>>>>> >>>>>> d_codd_64ch_2_10G_10GBE2_gbe00/d_codd_64ch_2_10G_10GBE2_gbe00/tge_tx_inst/tx_packet_fifo_inst/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.SINGLE_PRIM36.TDP >>>>>> >>>>>> (RAM) >>>>>> Requirement: 5.000ns >>>>>> Data Path Delay: 5.721ns (Levels of Logic = 1) >>>>>> Clock Path Skew: 0.054ns (2.112 - 2.058) >>>>>> Source Clock: adc0_clk rising at 0.000ns >>>>>> Destination Clock: adc0_clk rising at 5.000ns >>>>>> Clock Uncertainty: 0.060ns >>>>>> >>>>>> Clock Uncertainty: 0.060ns ((TSJ^2 + DJ^2)^1/2) / 2 >>>>>> + PE >>>>>> Total System Jitter (TSJ): 0.070ns >>>>>> Discrete Jitter (DJ): 0.097ns >>>>>> Phase Error (PE): 0.000ns >>>>>> >>>>>> Maximum Data Path at Slow Process Corner: >>>>>> >>>>>> d_codd_64ch_2_10G_10GBE2_gbe00/d_codd_64ch_2_10G_10GBE2_gbe00/tge_tx_inst/app_tx_validR >>>>>> >>>>>> to >>>>>> >>>>>> d_codd_64ch_2_10G_10GBE2_gbe00/d_codd_64ch_2_10G_10GBE2_gbe00/tge_tx_inst/tx_packet_fifo_inst/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.SINGLE_PRIM36.TDP >>>>>> >>>>>> >>>>>> Location Delay type Delay(ns) Physical >>>>>> Resource >>>>>> Logical >>>>>> Resource(s) >>>>>> ---------------------------------------------------- >>>>>> ------------------- >>>>>> SLICE_X81Y192.CQ Tcko 0.337 >>>>>> >>>>>> d_codd_64ch_2_10G_10GBE2_gbe00/d_codd_64ch_2_10G_10GBE2_gbe00/tge_tx_inst/app_tx_validR >>>>>> >>>>>> >>>>>> >>>>>> d_codd_64ch_2_10G_10GBE2_gbe00/d_codd_64ch_2_10G_10GBE2_gbe00/tge_tx_inst/app_tx_validR >>>>>> >>>>>> >>>>>> SLICE_X23Y278.A6 net (fanout=5) 4.173 >>>>>> >>>>>> d_codd_64ch_2_10G_10GBE2_gbe00/d_codd_64ch_2_10G_10GBE2_gbe00/tge_tx_inst/app_tx_validR >>>>>> >>>>>> >>>>>> SLICE_X23Y278.A Tilo 0.068 >>>>>> >>>>>> d_codd_64ch_2_10G_10GBE2_gbe00/d_codd_64ch_2_10G_10GBE2_gbe00/tge_tx_inst/tx_packet_fifo_inst/BU2/U0/grf.rf/ram_wr_en >>>>>> >>>>>> >>>>>> >>>>>> d_codd_64ch_2_10G_10GBE2_gbe00/d_codd_64ch_2_10G_10GBE2_gbe00/tge_tx_inst/tx_packet_fifo_inst/BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1 >>>>>> >>>>>> >>>>>> RAMB36_X1Y54.WEAU3 net (fanout=16) 0.628 >>>>>> >>>>>> d_codd_64ch_2_10G_10GBE2_gbe00/d_codd_64ch_2_10G_10GBE2_gbe00/tge_tx_inst/tx_packet_fifo_inst/BU2/U0/grf.rf/ram_wr_en >>>>>> >>>>>> >>>>>> RAMB36_X1Y54.CLKARDCLKU Trcck_WEA 0.515 >>>>>> >>>>>> d_codd_64ch_2_10G_10GBE2_gbe00/d_codd_64ch_2_10G_10GBE2_gbe00/tge_tx_inst/tx_packet_fifo_inst/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.SINGLE_PRIM36.TDP >>>>>> >>>>>> >>>>>> >>>>>> d_codd_64ch_2_10G_10GBE2_gbe00/d_codd_64ch_2_10G_10GBE2_gbe00/tge_tx_inst/tx_packet_fifo_inst/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.SINGLE_PRIM36.TDP >>>>>> >>>>>> >>>>>> ---------------------------------------------------- >>>>>> --------------------------- >>>>>> Total 5.721ns (0.920ns >>>>>> logic, 4.801ns route) >>>>>> (16.1% >>>>>> logic, 83.9% route) >>>>>> >>>>>> >>>>>> Device Utilization Summary: >>>>>> >>>>>> Slice Logic Utilization: >>>>>> Number of Slice Registers: 183,328 out of 595,200 >>>>>> 30% >>>>>> Number used as Flip Flops: 183,197 >>>>>> Number used as Latches: 3 >>>>>> Number used as Latch-thrus: 0 >>>>>> Number used as AND/OR logics: 128 >>>>>> Number of Slice LUTs: 155,306 out of 297,600 >>>>>> 52% >>>>>> Number used as logic: 72,780 out of 297,600 >>>>>> 24% >>>>>> Number using O6 output only: 43,389 >>>>>> Number using O5 output only: 10,220 >>>>>> Number using O5 and O6: 19,171 >>>>>> Number used as ROM: 0 >>>>>> Number used as Memory: 56,297 out of 122,240 >>>>>> 46% >>>>>> Number used as Dual Port RAM: 1,904 >>>>>> Number using O6 output only: 1,376 >>>>>> Number using O5 output only: 4 >>>>>> Number using O5 and O6: 524 >>>>>> Number used as Single Port RAM: 0 >>>>>> Number used as Shift Register: 54,393 >>>>>> Number using O6 output only: 36,882 >>>>>> Number using O5 output only: 0 >>>>>> Number using O5 and O6: 17,511 >>>>>> Number used exclusively as route-thrus: 26,229 >>>>>> Number with same-slice register load: 9,024 >>>>>> Number with same-slice carry load: 17,205 >>>>>> Number with other load: 0 >>>>>> >>>>>> Slice Logic Distribution: >>>>>> Number of occupied Slices: 53,681 out of 74,400 >>>>>> 72% >>>>>> Number of LUT Flip Flop pairs used: 189,068 >>>>>> Number with an unused Flip Flop: 38,081 out of 189,068 >>>>>> 20% >>>>>> Number with an unused LUT: 33,762 out of 189,068 >>>>>> 17% >>>>>> Number of fully used LUT-FF pairs: 117,225 out of 189,068 >>>>>> 62% >>>>>> Number of slice register sites lost >>>>>> to control set restrictions: 0 out of 595,200 >>>>>> 0% >>>>>> >>>>>> A LUT Flip Flop pair for this architecture represents one LUT >>>>>> paired >>>>>> with >>>>>> one Flip Flop within a slice. A control set is a unique >>>>>> combination of >>>>>> clock, reset, set, and enable signals for a registered element. >>>>>> The Slice Logic Distribution report is not meaningful if the >>>>>> design is >>>>>> over-mapped for a non-slice resource or if Placement fails. >>>>>> OVERMAPPING of BRAM resources should be ignored if the design is >>>>>> over-mapped for a non-BRAM resource or if placement fails. >>>>>> >>>>>> IO Utilization: >>>>>> Number of bonded IOBs: 233 out of 840 27% >>>>>> Number of LOCed IOBs: 233 out of 233 >>>>>> 100% >>>>>> IOB Flip Flops: 112 >>>>>> Number of bonded IPADs: 70 >>>>>> Number of LOCed IPADs: 70 out of 70 >>>>>> 100% >>>>>> Number of bonded OPADs: 64 >>>>>> Number of LOCed OPADs: 64 out of 64 >>>>>> 100% >>>>>> >>>>>> Specific Feature Utilization: >>>>>> Number of RAMB36E1/FIFO36E1s: 392 out of 1,064 >>>>>> 36% >>>>>> Number using RAMB36E1 only: 392 >>>>>> Number using FIFO36E1 only: 0 >>>>>> Number of RAMB18E1/FIFO18E1s: 154 out of 2,128 7% >>>>>> Number using RAMB18E1 only: 154 >>>>>> Number using FIFO18E1 only: 0 >>>>>> Number of BUFG/BUFGCTRLs: 9 out of 32 28% >>>>>> Number used as BUFGs: 9 >>>>>> Number used as BUFGCTRLs: 0 >>>>>> Number of ILOGICE1/ISERDESE1s: 141 out of 1,080 >>>>>> 13% >>>>>> Number used as ILOGICE1s: 77 >>>>>> Number used as ISERDESE1s: 64 >>>>>> Number of OLOGICE1/OSERDESE1s: 35 out of 1,080 3% >>>>>> Number used as OLOGICE1s: 35 >>>>>> Number used as OSERDESE1s: 0 >>>>>> Number of BSCANs: 0 out of 4 0% >>>>>> Number of BUFHCEs: 0 out of 216 0% >>>>>> Number of BUFIODQSs: 0 out of 108 0% >>>>>> Number of BUFRs: 5 out of 54 9% >>>>>> Number of LOCed BUFRs: 2 out of 5 40% >>>>>> Number of CAPTUREs: 0 out of 1 0% >>>>>> Number of DSP48E1s: 608 out of 2,016 >>>>>> 30% >>>>>> Number of EFUSE_USRs: 0 out of 1 0% >>>>>> Number of FRAME_ECCs: 0 out of 1 0% >>>>>> Number of GTXE1s: 32 out of 36 88% >>>>>> Number of IBUFDS_GTXE1s: 3 out of 18 16% >>>>>> Number of ICAPs: 0 out of 2 0% >>>>>> Number of IDELAYCTRLs: 4 out of 27 14% >>>>>> Number of IODELAYE1s: 64 out of 1,080 5% >>>>>> Number of MMCM_ADVs: 3 out of 18 16% >>>>>> Number of PCIE_2_0s: 0 out of 2 0% >>>>>> Number of STARTUPs: 1 out of 1 >>>>>> 100% >>>>>> Number of SYSMONs: 0 out of 1 0% >>>>>> Number of TEMAC_SINGLEs: 1 out of 4 25% >
