Thanks Jack and David
Both of those are what I am looking for. The PlanAhead output a .bin not .bit and the ucf file yellow block. One other question that has come up while looking at the ucf file is that xilinx by default groups all of the clocks in the design into one clock group. This seems to imply that all of the clocks have a synchronous relationship which is not true. In our case, we are running the MKID DAC/ADC board which provides the external clock to the FPGA and that is what we are running the FPGA core clock off of. Have you tried to change this relationship and break the clock domains up into truly different asynchronous clock groups? I am also concerned that the clock group is the only timing constraint present in the file. I am hoping that someone may have a more functional timing constraint file with realistic timing constraints. For the yellow block you are talking about I may have to merge some changes over because that block is not present in the mlib-devel I have been working with. The git I have been working from is http://github.com/casper-astro/mlib_devel.git from a little over a year ago. I will look into a more updated github repo that people have been working with. Johnathon Gard NIST
