Hello Yunpeng,

Black boxing can help speed up compile time but the place-and-route needs
to run every time, so it won't really help the design meet timing. In my
experience that's the thing that takes long.

Good luck.

Regards,
James




On Mon, Jun 5, 2017 at 9:58 AM, Vereese Van Tonder <vere...@ska.ac.za>
wrote:

> Hi Yunpeng,
>
> You can try "Black Boxing" parts of your design, that you know works.
> There's a tutorial on the CASPER wiki here:
>
> https://casper.berkeley.edu/wiki/Tutorial_HDL_Black_Box
>
> I hope this helps.
>
>
> On Sun, Jun 4, 2017 at 4:43 AM, 门云鹏 <yp...@pku.edu.cn> wrote:
>
>> Hi James, Michael, and Vereese,
>>
>> Thanks for your reply. I have read the timing report to find the failing
>> paths, and tried to add delay blocks or increasing adder / multiplier
>> latency. It works well but not always, especially for timing errors in some
>> yellow blocks, for instance
>>
>> I will try SmartXplorer and PlanAead, and see if they work.
>>
>> What's more, the casper_xps toolflow often takes a few hours, which makes
>> me crazy (>﹏<). I guess this is because timing constraints are difficult
>> to meet. I wonder if there is any good method to accelerate the xps
>> toolflow. (Map uses 2 processors, and par uses 4 processors by default. The
>> cpu is @2.70GHz 8M)
>>
>> Thank you all again,
>>
>> Yunpeng
>>
>>
>>
>> ------------------------------------------------------------
>> -----------------------
>> Yunpeng Men
>> PhD student
>> Department of Astronomy & Kavli Institute for Astronomy and
>> Astrophysics, Peking University
>> Yi He Yuan Lu 5, Hai Dian Qu, Beijing 100871, P. R. China
>>
>> -----原始邮件-----
>> *发件人:*"James Smith" <jsm...@ska.ac.za>
>> *发送时间:*2017-06-04 01:44:39 (星期日)
>> *收件人:* "Michael D'Cruze" <michael.dcr...@postgrad.manchester.ac.uk>
>> *抄送:* "门云鹏" <yp...@pku.edu.cn>, "casper@lists.berkeley.edu" <
>> casper@lists.berkeley.edu>
>> *主题:* Re: [casper] timing errors
>>
>>
>> Hello Yunpeng,
>>
>> Just to echo what Michael and Vereese said - those tools can help you get
>> a bit more insight into what's going on, and how badly your timing problem
>> is, but the timing report should tell you how by how much you're missing
>> timing (should be some nanosecond value).
>>
>> If it's just a small amount then sprinkling a few delay blocks in-between
>> major sections of your design, or increasing adder / multiplier latency in
>> your DSP blocks can usually help.
>>
>> Regards,
>> James
>>
>>
>> On Sat, Jun 3, 2017 at 6:54 PM, Michael D'Cruze <
>> michael.dcr...@postgrad.manchester.ac.uk> wrote:
>>
>>> Hi Yunpeng, all,
>>>
>>>
>>>
>>> I recently wrote a memo which describes how you can use Xilinx
>>> SmartXplorer to help with timing issues. Have a look on the casper wiki in
>>> the Memos section: https://casper.berkeley.edu/wi
>>> ki/images/f/f8/SmartXplorer_memo.pdf . It isn’t a free pass – you need
>>> to get fairly close using knowledge of individual hardware types on the
>>> FPGA, and you need to space out your design reasonably, by using pipelines.
>>> But it should help get over the final hurdle if you’re doing a reasonable
>>> job initially.
>>>
>>>
>>>
>>> Best,
>>>
>>> Michael
>>>
>>>
>>>
>>> *From:* 门云鹏 [mailto:yp...@pku.edu.cn]
>>> *Sent:* 03 June 2017 16:00
>>> *To:* casper@lists.berkeley.edu
>>> *Subject:* [casper] timing errors
>>>
>>>
>>>
>>> Dear all,
>>>
>>> I am using ROACH2 to develop digital receiving backend, but I often 
>>> encounter timing errors when I run casper_xps toolflow. I wonder if there 
>>> is any general solution to these timing errors.
>>>
>>> Thanks a lot,
>>>
>>> Yunpeng
>>>
>>>
>>>
>>> ------------------------------------------------------------
>>> -----------------------
>>>
>>> Yunpeng Men
>>>
>>> PhD student
>>>
>>> Department of Astronomy & Kavli Institute for Astronomy and
>>> Astrophysics, Peking University
>>>
>>> Yi He Yuan Lu 5, Hai Dian Qu, Beijing 100871, P. R. China
>>>
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>
>
> --
> Kind Regards,
> Vereesé
>

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