Hi Jack, Brian and Hong, Thanks for the excellent work and effort - well done to VCU118 team. The development team at SARAO are using Matlab 2018a and Vivado 2018.2 for SKARAB. Further porting effort on this board could be done during the Hardware Porting Workshop taking place later this year in order to address those caveats, especially the upload_to_ram_and_program() caveat.
Kind regards, Adam Isaacson South African Radio Astronomy Observatory (SARAO) Hardware Manager Cell: (+27) 825639602 Tel: (+27) 215067300 email: aisaac...@ska.ac.za On Tue, Jan 15, 2019 at 7:43 AM Jack Hickish <jackhick...@gmail.com> wrote: > Since you asked :) > > This incorporates the 1gbe core which Brian got running on the VCU. All I > did was massage the microblaze code we use on SNAP such that it can use > this interface, for its comms. In fact, this is part of a broader attempt > to harmonize the various Ethernet cores Casper provide such that they all > have the same software interface. Hopefully now the microblaze code is > generic it should "trivially" work with the upcoming 40/100G interface. > > J > > On Mon, 14 Jan 2019, 7:26 pm Dan Werthimer, <d...@ssl.berkeley.edu> wrote: > >> >> >> jack, >> >> did you do all this work? >> hong ? brian ? >> >> dan >> >> >> On Mon, Jan 14, 2019 at 7:23 PM Jack Hickish <jackhick...@gmail.com> >> wrote: >> >>> Hi CASPERites, >>> >>> I know a few of you have been playing around with the VCU118 Virtex >>> Ultrascale Plus dev board. For a while the toolflow has been able to >>> compile designs for this board, but without any support for accessing the >>> software registers / brams in the generated bitstream (making the toolflow >>> effectively useless). >>> >>> The VCU118 branch of mlib_devel -- >>> https://github.com/casper-astro/mlib_devel/tree/vcu118 -- now supports >>> compiling a VCU118 design with an embedded microblaze core, which allows >>> you to talk to the board using the standard casperfpga library. >>> >>> Note the following caveats -- >>> >>> - use the latest version of casperfpga ( >>> https://github.com/casper-astro/casperfpga, currently at commit ee9c43f >>> ) and install the dependencies with `pip install -r requirements.txt` >>> before installing casperfpga with `python setup.py install`. I strongly >>> recommend using a python virtual environment to be sure you are using the >>> right libraries. Note that the dependencies include a custom tftpy **not >>> the one obtained with `pip install tftpy`. >>> - casperfpga comms are (currently) only supported through the VCU118's >>> 1GbE RJ45 port >>> - You must instantiate a 1GbE yellow block in your design - see >>> https://github.com/casper-astro/mlib_devel/blob/vcu118/jasper_library/test_models/test_onegbe.slx >>> for a simple example >>> - You must check the "enable microblaze" checkbox in the VCU118 >>> configuration block. >>> - I tested using MATLAB 2017b and Vivado 2018.2. Use other versions of >>> software at your own risk. In particular, other versions of Vivado will >>> probably fail spectacularly. >>> - Your VCU118 will attempt to DHCP an IP address on boot. It has the MAC >>> address 02:03:04:05:01:18 . Once DHCP is complete, you should be able to >>> ping the board. >>> - Debugging information can be obtained on the VCU's USB UART port, with >>> your serial interface set to 115200 8N1. >>> - You must program the bitstream generated by the toolflow manually via >>> JTAG in vivado (the bitstream can be found at >>> <build-directory>/myproj/myproj.runs/impl_1/top.bit). casperfpga's >>> upload_to_ram_and_program command **will NOT work**. >>> >>> There is still a bunch of work to do to support this board -- for >>> example: supporting writing an image to the onboard flash, getting a unique >>> per-board MAC address, supporting other peripherals (notably 100GbE, which >>> some CASPERites are already working on, and an FMC ADC from ASIAA), etc. >>> etc. But for now, hopefully this zeroth-order support will help with other >>> yellow block development efforts, by allowing you to probe the board >>> without resorting to the joy of the vivado logic analyzer. >>> >>> Further help always appreciated, and feel free to shout when the above >>> doesn't work for you. >>> >>> Jack >>> >>> -- >>> You received this message because you are subscribed to the Google >>> Groups "casper@lists.berkeley.edu" group. >>> To unsubscribe from this group and stop receiving emails from it, send >>> an email to casper+unsubscr...@lists.berkeley.edu. >>> To post to this group, send email to casper@lists.berkeley.edu. >>> >> -- >> You received this message because you are subscribed to the Google Groups >> "casper@lists.berkeley.edu" group. >> To unsubscribe from this group and stop receiving emails from it, send an >> email to casper+unsubscr...@lists.berkeley.edu. >> To post to this group, send email to casper@lists.berkeley.edu. >> > -- > You received this message because you are subscribed to the Google Groups " > casper@lists.berkeley.edu" group. > To unsubscribe from this group and stop receiving emails from it, send an > email to casper+unsubscr...@lists.berkeley.edu. > To post to this group, send email to casper@lists.berkeley.edu. > -- You received this message because you are subscribed to the Google Groups "casper@lists.berkeley.edu" group. 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