Dear Aravind, I have fixed your slx file - see attached. There were a few issues:
1) sw_reg reg_cntrl yellow block bitfield type was not set to boolean 2) your snapshot, adc_in_snap, was not setup correctly. You have to manually add the names in the snapshot fields - double click on the snapshot and see "input" tab 3) Your adc_sample_ctr was set to 9 bits and not 32 bits. It should compile fine now. My advice is that if you are struggling to get your slx file to compile, then look at the completed design slx file in github and make sure your design matches that. There is a completed slx model and working fpg file for each tutorial. Kind regards, Adam Isaacson South African Radio Astronomy Observatory (SARAO) Hardware Manager Cell: (+27) 825639602 Tel: (+27) 215067300 email: aisaac...@ska.ac.za On Tue, Apr 7, 2020 at 10:28 AM Adam Isaacson <aisaac...@ska.ac.za> wrote: > Dear Aravind, > > Did you know there is an existing, working and completed slx file > (tut_adc_dac.slx) for this tutorial in: > > > https://github.com/casper-astro/tutorials_devel/tree/master/red_pitaya/tut_adc_dac > > I would compare that file with your file attached and look for any > differences. I am also going to look at your file and see if I can spot > anything. Stay tuned. > > Kind regards, > > Adam Isaacson > South African Radio Astronomy Observatory (SARAO) > Hardware Manager > Cell: (+27) 825639602 > Tel: (+27) 215067300 > email: aisaac...@ska.ac.za > > > > On Tue, Apr 7, 2020 at 1:53 AM Aravind Venkitasubramony < > arve9...@colorado.edu> wrote: > >> Hi >> >> I followed the tutorial and created the .slx file. While compiling I got >> these errors from simulink. >> >> >> Matching "From" for "Goto" 'rp_tut2/adc_in_snap/ss/goto_ss_we1' not found >> [4 similar] >> Component:Simulink | Category:Block warning >> Output port 1 of 'rp_tut2/dac/rp_tut2_dac_dac0_data_i_in' is not >> connected. [8 similar] >> Component:Simulink | Category:Block warning >> The input type propagated to this block did not match the specified type. >> Expected Type: Bool >> Actual Type: Fix_10_0 >> >> Error occurred during "Rate and Type Error Checking". >> >> >> Reported by: >> 'rp_tut2/adc_in_snap/assert_b' >> A summary of Sysgen errors has been written to >> '/home/cet/RP_work/models/rp_tut2/rp_tut2_sysgen_error.log' >> >> Reported by: >> 'rp_tut2/adc_in_snap/assert_b' >> >> I also notice that I do not get the "in_adc_data_valid" port shown in the >> in the bit field snap block on the tutorial page. Other than that, I >> recreated everything as mentioned in the tutorial page. I have attached the >> .slx and the sysgen error log files also alongwith >> >> -- >> You received this message because you are subscribed to the Google Groups >> "casper@lists.berkeley.edu" group. >> To unsubscribe from this group and stop receiving emails from it, send an >> email to casper+unsubscr...@lists.berkeley.edu. >> To view this discussion on the web visit >> https://groups.google.com/a/lists.berkeley.edu/d/msgid/casper/ddcf80a1-1118-4262-94a1-1e7cc66f0056%40lists.berkeley.edu >> <https://groups.google.com/a/lists.berkeley.edu/d/msgid/casper/ddcf80a1-1118-4262-94a1-1e7cc66f0056%40lists.berkeley.edu?utm_medium=email&utm_source=footer> >> . >> > -- You received this message because you are subscribed to the Google Groups "casper@lists.berkeley.edu" group. To unsubscribe from this group and stop receiving emails from it, send an email to casper+unsubscr...@lists.berkeley.edu. To view this discussion on the web visit https://groups.google.com/a/lists.berkeley.edu/d/msgid/casper/CADTJ%3DnFCBeu6L8r5Rc14hGQ8UX2M6b8dX%3DbfEqOgk5XsRnv76g%40mail.gmail.com.
rp_tut2.slx
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