Hi Kaj, To follow on to Mitch's mention of licensing issues, you may want to put together a simple design in Vivado itself and try run synth and implementation there - if it's a licensing issue, the Vivado log will give you more info. Or check the Vivado licence manager to make sure you have the correct IP licences. Unfortunately the Simulink sysgen errors are kinda unhelpful when it comes to this kind of thing, and so you need to do some digging to track down what it's missing.
Morag On Tue, 21 Feb 2023, 18:22 Mitchell Burnett, <mitch.c.burn...@gmail.com> wrote: > Kaj,When installing Vivado, at the installation configuration window there > is a drop down for installing RFSoC engineering silicon parts. This needs > to be selected. The default parts in the toolflow are engineering silicon > (ES). Probably bad defaults now that when you buy a > 216/2 > > > > > > > > > > > > > > > > > > > > > > > > > > > <https://za.report.cybergraph.mimecast.com/alert-details/?dep=ysA%2BrK76%2FS%2Byy04cnPE6sA%3D%3DExE48bU0i8x19sn%2FR1K%2FC%2BsDjT2%2FdLyqCaWcCcGPCSJzIFCYEPxK%2BL2AOBsCcLhxw2VGQEdttNt8dDDLqDTwel8dEkW68rkUB%2F9PiSz9JMbygDD%2Bjhh8gMKcA2je6nE5jAqpXFj2pJxfngsze8lgInnGruCn%2BkM%2B9GH5uaphWe2WjXPJ%2B%2BNbw5dl%2F2gYRPFAe9T0ho3Ys%2FUP7g0jUpFOkjqOm4fho15CrXI4T9SPRGg1cgzeZd6SpucLmHLA5CqdP9WJvbA3A52isjt5eVfMQBsx4rgzq%2FsYF4C0fv4PR%2FlJspL7UtZSYA82ZjY2oAwOnLlBLXLWzF0Vh4xeQcv00lxTB77V22a%2FK2QQONBwfDPV76GO9lnkvsa2Qqe%2FF3FTOwsfSEvfmHIkcTc4NLKBEAQVMmCt%2BOTAtBY84Ehq9hfcE6GAgTYOUX72LuAjwIN8MNXIPlS4lt%2FZTwyJyM3s%2FsYVkRCAyeOjP71T34OiS9MMJVVwdbWT7Nb8CcLMsxL%2BPG6RYXR6K1x1uajyqdYDGCYSFcvKu0n24SG5gQ%2B%2BThOw5jzYjAXPlrR6ICayptpoxjqdTG4BjKMmF9EQmGRr6g%3D%3D> > Kaj, > > When installing Vivado, at the installation configuration window there is > a drop down for installing RFSoC engineering silicon parts. This needs to > be selected. The default parts in the toolflow are engineering silicon > (ES). Probably bad defaults now that when you buy a 216/208 or any other > 48/49dr boards they will come with production silicon. But, I only have ES > and so I have never changed it. > > To change this, and not use ES parts, you would need to update the `fpga` > key in the the yaml platform file and remove the `-es1` suffix. > (`mlib_devel/jasper_library/platforms/zcu216.yaml). > > Regarding your other errors. I have only ever really seen these when > having license issues. The message never really shows when it is a license > problem. It is more explicitly stated in the simulink log file that > simulink points you too in the diagnostic viewer. If it isn’t licensing, > then I am not really sure. > > Mitch > > On Feb 21, 2023, at 8:13 AM, Kaj Wiik <kjw...@utu.fi> wrote: > > Hi! > > As a test I made a design with only sysgen, ZCU111 and rfdc block and I > got the same > > ---------------------------- > > The S-function 'sysgen' in > 'sysgen_only/rfdc/sysgen_only_rfdc_s00_axis_tdata' has specified the option > SS_OPTION_PORT_SAMPLE_TIMES_ASSIGNED and specified inherited for sample > time number 0. Inheriting a sample time is not supported when specifying > SS_OPTION_PORT_SAMPLE_TIMES_ASSIGNED > > ---------------------------- > > error without any connections. The same error message with ZRF16. When I > am trying with ZCU216 or ZCU208, I get an error message that these parts > are not in my Vivado installation, according to release notes, they should > be (maybe an error in the part suffix?). > > When I ran update_casper_blocks(bdroot), I got > > ---------------------------- > ... > searching for CASPER blocks to update in sysgen_only...found 2 > updating block sysgen_only/ZCU111... > updating block sysgen_only/rfdc... > Error using update_casper_block (line 216) > Invalid setting in Xilinx RF Data Converter block (mask) 'rfdc' for > parameter 't228_DT_dac1_mixer_mode' > > Error in update_casper_blocks (line 140) > update_casper_block(blks{k}); - Show complete stack trace > ---------------------------- > > and the rfdc block disappeared... DAC was disabled. > > This cannot be due to using Ubuntu 18.04 surely? > > Any suggestions what to try next? > > Thanks, > Kaj > > ---------------------------- > > (base) kjwiik@rfsoc:~/casper/mlib_devel$ git status > On branch m2021a > Your branch is up to date with 'origin/m2021a'. > > (base) kjwiik@rfsoc:~/casper/xilinx/device-tree-xlnx$ git status > On branch master > Your branch is up to date with 'origin/master'. > > > > > > On 2/20/23 18:12, Kaj Wiik wrote: > > Hi! > An update... > The segfault was (fortunately!) due to Ubuntu 20.04 running a 18.04 kernel > (Linux System Containers). > I moved then to 18.04 container, I had to install miniconda3 to get more > recent Python, after that I was able to produce bitstream without errors > from the > zcu111_tut_platform.slx > I then tried zcu216_tut_spec.slx but it was stuck to endless error > messages about "Part not found in Vivado" (attached). The same with > zcu216_tut_spec_cx.slx > zcu111_tut_rfdc gave these errors: > ---------------------------------- > The input ports on this block must be driven by other Xilinx blocks > Reported by: > 'zcu111_tut_rfdc/rfdc/rfdc_rfdc_s00_axis_tdata' > The input ports on this block must be driven by other Xilinx blocks > Reported by: > 'zcu111_tut_rfdc/rfdc/rfdc_rfdc_s01_axis_tdata' > A summary of Sysgen errors has been written to > '/home/kjwiik/casper/tutorials_devel/rfsoc/tut_rfdc/zcu111_tut_rfdc_sysgen_error.log' > Reported by: > 'zcu111_tut_rfdc/rfdc/rfdc_rfdc_s00_axis_tdata' > The S-function 'sysgen' in 'zcu111_tut_rfdc/ain/io_delay' has specified > the option SS_OPTION_PORT_SAMPLE_TIMES_ASSIGNED and specified inherited for > sample time number 0. Inheriting a sample time is not supported when > specifying SS_OPTION_PORT_SAMPLE_TIMES_ASSIGNED > ---------------------------------- > I guess these tutorials have been verified in some setups, clearly I am > now missing something. Are these due to my FrankenCasper setup or am I > using a wrong version of ... something? > Ubuntu 18.04 with Python 3.8.16 from miniconda > Using MATLAB_PATH=/opt/MATLAB/R2021a > Using XILINX_PATH=/opt/Xilinx/Vivado/2021.1 > Using COMPOSER_PATH=/opt/Xilinx/Model_Composer/2021.1 > ENVIRONMENT INFO: > Model Composer Bin Dir : /opt/Xilinx/Model_Composer/2021.1/bin > Vitis Bin Dir : /opt/Xilinx/Vitis/2021.1/bin > System Generator Bin Dir : /opt/Xilinx/Vivado/2021.1/bin > Thanks, > Kaj > On 2/19/23 12:47, Kaj Wiik wrote: > > Hi! > > After setting > > numpy<1.20 > > in requirements.txt and doing this (copying it here because the link was > broken yesterday!): > > > https://docs.xilinx.com/r/2021.2-English/ug1483-model-composer-sys-gen-user-guide/Supported-MATLAB-Versions-and-Operating-Systems > <https://docs.xilinx.com/r/2021.2-English/ug1483-model-composer-sys-gen-user-guide/Supported-MATLAB-Versions-and-Operating-Systems> > ------------------------- > Prerequisites for using Model Composer on Ubuntu 20 OS > > QT4 library should be installed. > Ubuntu 20 comes with gcc 7.x to 9.x versions by default; you need to > either install gcc 6.x manually or create a symbolic link using the > following sudo commands: > sudo ln -s /usr/include/asm-generic /usr/include/asm > sudo ln -s /usr/include/x86_64-linux-gnu/sys /usr/include/sys > sudo ln -s /usr/include/x86_64-linux-gnu/bits /usr/include/bits > sudo ln -s /usr/include/x86_64-linux-gnu/gnu /usr/include/gnu > Ubuntu 20 by default comes with dash shell. To avoid any issue that you > may encounter while running the downstream AI Engine flows, it is > recommended to change the shell from dash to bash using the following sudo > command: > sudo dpkg-reconfigure dash > -------------------------- > > I can simulate zcu111_tut_platform but jasper stops to a segfault: > > -------------------------- > .... > # update_compile_order -fileset sources_1 > # reset_run synth_1 > # launch_runs synth_1 -jobs 4 > INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP > 'zcu111_tut_platform_ip'... > tcmalloc: large alloc 31648768670588928 bytes == (nil) @ 0x7fa5dd50a644 > 0x7fa57d6b133d > Abnormal program termination (11) > Please check '/home/kjwiik/work/zcu111_tut_platform/hs_err_pid19590.log' > for details > segfault in /opt/Xilinx/Vivado/2021.1/bin/unwrapped/lnx64.o/vivado -exec > vivado -jou /home/kjwiik/work/zcu111_tut_platform/vivado.jou -log > /home/kjwiik/work/zcu111_tut_platform/vivado.log -mode batch -source > /home/kjwiik/work/zcu111_tut_platform/gogogo.tcl, exiting... > Traceback (most recent call last): > File "/home/kjwiik/work/mlib_devel/jasper_library/exec_flow.py", line > 239, in <module> > backend.compile(cores=opts.jobs, plat=platform, > File "/home/kjwiik/work/mlib_devel/jasper_library/toolflow.py", line > 2329, in compile > raise Exception('Vivado failed!') > Exception: Vivado failed! > Error using jasper (line 23) > Backend build failed! Check log files for more information > ---------------------------- > > I tried to replace libtcmalloc.so.4 from Matlab and Vivado/Vitis > installations with a libtcmalloc.so.4 from one in libgoogle-perftools4 but > got > > ---------------------------- > realloc(): invalid pointer > Abnormal program termination (6) > ---------------------------- > instead. > > There is this error in the start, maybe not related: > - > --------------------------- > ERROR: Could not get table row for block(tout), parent(77777) info( 0000 > 1111 2222 3333 4444 5555 6666 7777 8888 9999 .... .... .... .... .... .... > .... .... .... ....1024681246822468324684246852468624687246882468924680) > ---------------------------- > > I also tried to delete all except the led blinking blocks from the design > but still got the segfault. > > --------------------------------- Version Log > ---------------------------------- > Version Path > System Generator 2021.1 /opt/Xilinx/Vivado/2021.1 > Matlab 9.10.0.2015706 (R2021a) Update 7 /opt/MATLAB/R2021a > Vivado 2021.1 /opt/Xilinx/Vivado/2021.1 > Ubuntu 20.04 > > Any suggestions? > > Thanks, > Kaj > > > -- > You received this message because you are subscribed to the Google Groups " > casper@lists.berkeley.edu" group. > To unsubscribe from this group and stop receiving emails from it, send an > email to casper+unsubscr...@lists.berkeley.edu. > To view this discussion on the web visit > https://groups.google.com/a/lists.berkeley.edu/d/msgid/casper/0e015935-6b31-18b2-0477-179fbf6de51b%40utu.fi > <https://groups.google.com/a/lists.berkeley.edu/d/msgid/casper/0e015935-6b31-18b2-0477-179fbf6de51b%40utu.fi> > . > > > -- > You received this message because you are subscribed to the Google Groups " > casper@lists.berkeley.edu" group. > To unsubscribe from this group and stop receiving emails from it, send an > email to casper+unsubscr...@lists.berkeley.edu. > To view this discussion on the web visit > https://groups.google.com/a/lists.berkeley.edu/d/msgid/casper/CFAA5F94-D137-4CA9-A2F1-B1883965AC2A%40gmail.com > <https://groups.google.com/a/lists.berkeley.edu/d/msgid/casper/CFAA5F94-D137-4CA9-A2F1-B1883965AC2A%40gmail.com?utm_medium=email&utm_source=footer> > . > Disclaimer The information contained in this communication from the sender is confidential. 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