A ZCU216 was prepared with the CASPERized linux image and programmed with a bitstream. The bitstream was derived from tutorials_devel zcu216_tut_rfdc.slx with slight modification. (part of *Tutorial 2: The RFDC Interface.* ) A signal generator produced sinusoids of a fixed frequency and an RF splitter distributed the signal to independent RF channels.
The RFADC for the ZCU216 is a quadtile architecture. RF channels within the *same tile* exhibited synchronized phases in the signal data, as expected. However signals passing over channels within *different tiles* are still exhibiting misaligned phases. Our use-case requires perfect phase alignment over (at least) 8 channels, and we would prefer all 16 if possible. We suspect there may be something missing from our software pipeline in regards to MTS. (see e.g. appendix C of* "On Algorithmic Design Methodologies,Heterogenous RFSoC/GPU Beamformer, and",* (2023)) prg_clk104_rfpll was used with a register file shown, and resulted in these ADC states (below) On Thursday, July 31, 2025 at 5:03:48 PM UTC-4 Ken Semanov wrote: > (creating this thread since former was dropped by google) -- You received this message because you are subscribed to the Google Groups "casper@lists.berkeley.edu" group. To unsubscribe from this group and stop receiving emails from it, send an email to casper+unsubscr...@lists.berkeley.edu. To view this discussion visit https://groups.google.com/a/lists.berkeley.edu/d/msgid/casper/48e4b8b5-b5aa-4777-9c3f-e8950e362dd7n%40lists.berkeley.edu.
