['rfdc']
.init() returned True
ADC0: Enabled 1, State: 6 PLL: 0
ADC1: Enabled 1, State: 6 PLL: 0
ADC2: Enabled 1, State: 6 PLL: 0
ADC3: Enabled 1, State: 6 PLL: 0
using ['250M_PL_125M_SYSREF_10M.txt']
ADC0: Enabled 1, State: 15 PLL: 1
ADC1: Enabled 1, State: 15 PLL: 1
ADC2: Enabled 1, State: 15 PLL: 1
ADC3: Enabled 1, State: 15 PLL: 1
"Enable Multi-Tile Sync" was checked for all tiles. System clocking config
is shown below. (disregard greyed-out elements. We can un-grey them with
trivial changes.)
Since google appears to block images, The following is reproduced in text
instead.
Tile 224
[x] Enable Tile
Clocking and PLL Configuration
[x] Enable Multi-Tile Sync
Sampling Rate (Mbps) 2000 Clock Out (MHz) 125
[x] Enable Tile PLLs
Required AXI4-Stream Clock (MHz) 250
Quad tile Configuration
ADC Pair 0,1
ADC 0
[x] Enable ADC
Data Settings
(et cetera)
-----
Parameters
System Clocking
ADC Tile 0 [ ] Has Clock Clock Source Tile 226 Distribute Clock None
ADC Tile 1 [x] Has Clock Clock Source Tile 226 Distribute Clock None
ADC Tile 2 [x] Has Clock Clock Source Tile 226 Distribute Clock
Input Rfclk
ADC Tile 3 [ ] Has Clock Clock Source Tile 226 Distribute Clock None
------------
(contents of zcu216.yaml)
rfdc:
tile224:
has_adc_clk: True
adc_clk_src: 2
tile225:
has_adc_clk: True
adc_clk_src: 2
tile226:
has_adc_clk: True
adc_clk_src: 2
tile227:
has_adc_clk: True
adc_clk_src: 2
On Thursday, July 31, 2025 at 5:03:48 PM UTC-4 Ken Semanov wrote:
> (creating this thread since former was dropped by google)
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