Hi Vinay,
I faced the same issue exactly and had same increasing slip errors.
Kindly make one side as ISDN network as te default setting is ISDN user
side.
Use below command :
Int s0/0/0:15
isdn emulate-protocol network
Regards,
Wael Agina
2011/2/24 Roger Källberg <roger.kallb...@cygate.se>
> Please post appropriate parts of your config, that makes it so much easier
> to help you ;)
>
> ** Sent from my iPhone. Excuse brevity and typographical errors. **
>
> 24 feb 2011 kl. 19:20 skrev "ccie_voice-requ...@onlinestudylist.com" <
> ccie_voice-requ...@onlinestudylist.com>:
>
> Send CCIE_Voice mailing list submissions to
> <ccie_voice@onlinestudylist.com>ccie_voice@onlinestudylist.com
>
> To subscribe or unsubscribe via the World Wide Web, visit
> <http://onlinestudylist.com/mailman/listinfo/ccie_voice>
> http://onlinestudylist.com/mailman/listinfo/ccie_voice
> or, via email, send a message with subject or body 'help' to
> <ccie_voice-requ...@onlinestudylist.com>
> ccie_voice-requ...@onlinestudylist.com
>
> You can reach the person managing the list at
> <ccie_voice-ow...@onlinestudylist.com>
> ccie_voice-ow...@onlinestudylist.com
>
> When replying, please edit your Subject line so it is more specific
> than "Re: Contents of CCIE_Voice digest..."
>
> <Today's Topics (1 messages)>
>
> Hi,
>
> I have connected two routers Back-to-Back using the E1 Cross over cable,
> but I am unable to get the *Multiple_Frame_Established.*
>
> I see on one of the side as slips are increasing, I tried to change the
> Clock source to Internal.
>
>
> *E1 0/1/0 is up.*
> *Applique type is Channelized E1 - balanced*
> * No alarms detected.*
> * alarm-trigger is not set*
> * Version info Firmware: 20090113, FPGA: 20, spm_count = 0*
> * Framing is NO-CRC4, Line Code is HDB3, Clock Source is Internal.*
> * CRC Threshold is 320. Reported from firmware is 320.*
> * Data in current interval (287 seconds elapsed):*
> * 4 Line Code Violations, 1 Path Code Violations*
> * 1 Slip Secs, 0 Fr Loss Secs, 2 Line Err Secs, 0 Degraded Mins*
> * 3 Errored Secs, 0 Bursty Err Secs, 0 Severely Err Secs, 0 Unavail
> Secs*
>
>
> *E1 0/2/0 is up.*
> * Applique type is Channelized E1 - balanced*
> * No alarms detected.*
> * alarm-trigger is not set*
> * Version info Firmware: 20090113, FPGA: 20, spm_count = 0*
> * Framing is NO-CRC4, Line Code is HDB3, Clock Source is Line Primary.*
> * CRC Threshold is 320. Reported from firmware is 320.*
> * Data in current interval (137 seconds elapsed):*
> * 0 Line Code Violations, 0 Path Code Violations*
> * 29 Slip Secs, 0 Fr Loss Secs, 0 Line Err Secs, 0 Degraded Mins*
> * 29 Errored Secs, 0 Bursty Err Secs, 0 Severely Err Secs, 0 Unavail
> Secs*
>
>
> Warm Regards,
> Vinay Kumar
>
> <Digest Footer>
>
>
> _______________________________________________
> For more information regarding industry leading CCIE Lab training, please
> visit www.ipexpert.com
>
>
--
Thanks and Best Regards,
Wael Agina
_______________________________________________
For more information regarding industry leading CCIE Lab training, please visit
www.ipexpert.com
