On Nov 10, 2015 2:40 PM, "Brad Parker" <b...@heeltoe.com> wrote: > > > Don't you also need to "delayer" the chip to get all the hidden features? I thought the process of reconstructing the polygons required that each successive layer be exposed. From the "top" I'd think you'd only see a single metal layer. But then again, on a old chip like that there may only *be* one metal layer :-) > > My primitive understanding is that there will be a "base layer" with junctions and one or more metal layers on top doing the interconnect. > > (I try and steer clear of physical design, or "PD" as we call it, since it's seriously complex. but also interesting!) >
As a physical layout guy, you're absolutely correct. Some ICs can have tens of metal layers, and in order to have better yield, planarization is used, requiring fairly uniform metal density across all layers. This means adding metal fill where necessary, so that makes visualizing ICs much more difficult. Modern digital ICs typically rely on standard cell libraries, so that can make identification a little easier. Once you've identified one NAND gate or inverter, for instance, you've identified them all. Not so with the early designs that were more discrete, in that respect. These folks have done a lot of work related to this field: http://www.visual6502.org Kyle