> On Jun 7, 2017, at 3:24 PM, Chuck Guzis via cctech <cct...@classiccmp.org>
> wrote:
>
> On 06/07/2017 10:47 AM, Paul Koning via cctech wrote:
>
>> 6600 core memory is documented in great detail in the training manual
>> which is on Bitsavers. It has conventional diagonal sense lines. It
>> does have some interesting design attributes, though. For one thing,
>> it has pairs of inhibit wires each carrying half the inhibit current.
>> Also, there are four X inhibit and four Y inhibit lines, so you use
>> four of the address bits to select which inhibit "quadrant" is
>> driven. The manual doesn't say why; I believe it is done to limit
>> the inductance and to keep the per-wire inductance roughly consistent
>> for the select (X and Y) and inhibit (X and Y) wires. The drive
>> circuitry is also interesting, featuring constant currents that are
>> steered between an idling inductor and the selected wire, rather than
>> being switched on. All these techniques seem to explain the very
>> high performance -- full read/restore cycle in about 800 ns, which in
>> 1964 was way faster than what others were doing.
>
> How is ECS constructed? I fooled with a lot of it back in the day, but
> never got a good look at the core planes.
I'd love to know. I never saw the insides of ECS. There are some documents on
Bitsavers but none that I have seen show the ECS memory subsystem itself,
certainly not at the circuit level.
By the way, the memory chapter of the 6600 training manual is very much worth
reading carefully. It has some very clever circuits in it, and trying to
reason through in your head why things are done a certain way is a lot of fun.
paul
