I'm interested in the history of the logic design for the edge-triggered D flip-flop, as used in the SN7474. The design is composed of three set-reset latches (six NAND gates total) per flip-flop.
Does anyone know what year the SN7474 was introduced, or have an early datasheet for it (prior to the 1973 TTL Data Book For Design Engineers 1st Edition? The earliest datasheet I've found using this specific logic design for an edge-triggered D flip-flop is from a non-7400-series TTL chip, the Motorola MC3060/3160, which is a member of the MTTL III MC3000/MC3100 series.The MC3060 is covered in the Motorola 1968 IC databook, on page 4-138. I've searched US patents for edge-triggered flip-flop design, but have not found one specifically for the three S-R latch design. The subject came up as a result of a discussion on a private mailing list regarding the fact that the conventional J-K master-slave flip-flop design is NOT edge-triggered; pulses on J and/or K while the clock is high but stable can affect the Q (and not-Q) outputs of the FF at the following falling edge of the clock. That behavior is known as "pulse catching", and such a flip-flop is properly called pulse-triggered or level-triggered, but not edge-triggered. Early datasheets on J-K master-slave flip-flops actually had correct terminology and specifically stated that J and K should not change while the clock is high.
