On Wed, Sep 27, 2017 at 8:23 PM, Adrian Graham via cctalk <cctalk@classiccmp.org> wrote:
> Schematic for the circuits is here - > http://www.binarydinosaurs.co.uk/newbrainPowerupCircuits.png > <http://www.binarydinosaurs.co.uk/newbrainPowerupCircuits.png> - top circuit > is PWRUP and the bottom one is RESET that goes straight to the Z80. > CD4000 logic can't handle inputs pulled above the power pin or below the ground pin without the possibility of malfunctioning or even complete failure. Google for "CD4000 parasitic SCR" or "CMOS latch-up". When power is cycled rapidly, the caps will still have charge which could cause the latch-up. I did some industrial control designs with CD4000 and used similar timing circuits, but always included diodes to prevent inputs from being driven too high or too low. I would have put diodes across both of the resistors. Adding your probes may change the currents inside the chip that change the latch-up behavior. Of course it also only makes sense if the power is cycled quickly for some value of quickly. Others may have an explanation, but that was my first thought from looking at the schematic. -chuck
