Probably the factor that most think limits thing is the turn-around time. If they were limited to one byte request and wait for that data to return, the limits of wires would be a wall. Today's serial RAMs send a burts of data rather than a word or byte at a time. These blocks of data can use multiple serial lanes at one time where the data bits aren't even exactly arriving at the same time. There are FIFOs and parallelizers that bring things back together. The latency of the first fetch is slower than it used to be for traditional fetches but after that things are quite quick. Surprisingly, this is actually good for older languages like Forth that are fugal with RAM. Entire applications ( less data in some cases ) can be in the CPU's cache for immediate use. Dwight ________________________________ From: cctalk <cctalk-boun...@classiccmp.org> on behalf of Curious Marc via cctalk <cctalk@classiccmp.org> Sent: Saturday, January 5, 2019 9:40 PM To: Jeffrey S. Worley; General Discussion: On-Topic and Off-Topic Posts Subject: Re: OT? Upper limits of FSB
Interconnects at 28Gb/s/lane have been out for a while now, supported by quite a few chips. 56Gb/s PAM4 is around the corner, and we run 100Gb/s in the lab right now. Just sayin’ ;-). That said, we throw in about every equalization trick we know of, PCB materials are getting quite exotic and connectors are pretty interesting. We have to hand hold our customers to design their interconnect traces and connector breakouts. And you can’t go too far, with increasing reliance on micro-twinax or on-board optics for longer distances and backplanes. Marc > On Jan 4, 2019, at 11:02 PM, Jeffrey S. Worley via cctalk > <cctalk@classiccmp.org> wrote: > > Apropos of nothing, I've been confuse for some time regarding maximum > clock rates for local bus. > > My admittedly old information, which comes from the 3rd ed. of "High > Performance Computer Architecture", a course I audited, indicates a > maximum speed on the order of 1ghz for very very short trace lengths. > > Late model computers boast multi-hundred to multi gigahertz fsb's. Am > I wrong in thinking this is an aggregate of several serial lines > running at 1 to 200mhz? No straight answer has presented on searches > online. > > So here's the question. Is maximum fsb on standard, non-optical bus > still limited to a maximum of a couple of hundred megahertz, or did > something happen in the last decade or two that changed things > dramatically? I understand, at least think I do, that these > ridiculously high frequency claims would not survive capacitance issues > and RFI issues. When my brother claimed a 3.2ghz bus speed for his > machine I just told him that was wrong, impossible for practical > purposes, that it had to be an aggregate figure, a 'Pentium rating' > sort of number rather than the actual clock speed. I envision > switching bus tech akin to present networking, paralleled to sidestep > the limit while keeping pin and trace counts low.....? Something like > the PCIe 'lane' scheme in present use? This is surmise based on my own > experience. > > When I was current, the way out of this limitation was fiber-optics for > the bus. This was used in supercomputing and allowed interconnects of > longer length at ridiculous speeds. > > Thanks for allowing me to entertain this question. Though it is not > specifically a classic computer question, it does relate to development > and history. > > > > Best, > > Technoid Mutant (Jeff Worley) > > > > >
