> On Mar 5, 2021, at 9:02 PM, Johnny Billquist <b...@softjar.se> wrote:
>
> On 2021-03-06 02:33, Paul Koning wrote:
> ...
>> The explanation I heard for the slow J-11 clock is that the original J-11
>> spec called for it to operate at 20 MHz. When Harris failed to deliver and
>> the max useable clock speed ended up to be 18 MHz, most designs had no
>> trouble. But the Pro support chips were designed to run synchronous with
>> the CPU clock and for various other reasons needed a clock frequency that's
>> a multiple of 10 MHz, so when 20 MHz was ruled out that left 10 MHz as the
>> only alternative.
>
> I do think it sounds weird that the support chips would require a clock that
> is a multiple of 10 MHz. But I wouldn't know for sure.
> Somewhere else I read/heard that they didn't work reliable above 10 MHz, but
> for the F11 that was ok. When the -380 came, they just reused those support
> chips.
The 380 has an entirely different core design. Instead of lots of discrete
support chips including a pile of screwball Intel chips, it uses a pair of gate
arrays that incorporate all those functions. Or more precisely, the subset
that the OS actually needs. This is really obvious when you compare the 350
and 380 documentation for the interrupt controllers -- the 350 uses Intel
chips, the 380 only implements a tiny subset of what those chips do.
I'm guessing here, but a possible reason for the 10 MHz issue is if the support
chips use that clock, and use a synchronous design for the clock boundary
crossing rather than an asynchronous design. It's entirely possible to design
a chip that has an outside interface with an unrelated clock frequency, but
it's harder to do and harder to get right.
paul
