> On Apr 21, 2024, at 9:17 PM, Will Cooke via cctalk <cctalk@classiccmp.org>
> wrote:
>
>
>
>> On 04/21/2024 7:06 PM CDT Peter Coghlan via cctalk <cctalk@classiccmp.org>
>> wrote:
>>
>>
>>
>> Why is that? Did the Z80 take more cycles to implement it's more complex
>> instructions? Is this an early example of RISC vs CISC?
>>
>> Regards,
>> Peter Coghlan
>
> I'm certainly no authority, but I have programmed both processors in assembly
> and studied them somewhat. It took many years for me to believe that the
> 6502 was "faster" than the Z80, but now I'm (mostly) a believer. So here is
> my take.
>
> First, yes, the Z80 takes roughly 4 times as many clock cycles per
> instruction. Where the 6502 can complete a simple instruction in a single
> clock, the Z80 takes a minimum of four.
>
> The 02 certainly has a simpler architecture, but calling it a RISC machine
> would probably make the RISC believers cringe. It is simple, but it doesn't
> follow the pattern of lots of registers (well, maybe) and a load/store
> architecture. But that may be its strongest point. The zero page
> instructions effectively make the first 256 bytes of RAM into a large (128 or
> 256) register file.
> ...
Cycles per instruction is one aspect of RISC vs. CISC but there are more, and
cycles per instruction may not be the most significant one.
Given enough silicon and enough brainpower thrown at the problem, CISC machines
can be made to run very fast. Consider modern x86 machines for example. But
the key point is "given enough silicon...".
I think the significance of RISC isn't so much in cycles per instruction but
rather in simplicity of implementation (for a given level of performance).
It's not just single cycle instructions. In RISC architectures it is often
easier to achieve pipelining and parallelism. Consider what's arguably the
first example, the CDC 6600 with its parallelism, and its sibling the 7600
which made the rather obvious addition of pipelining.
Simplicity of implementation means either lower cost for a given level of
performance, or higher achievable performance for a given level of technology,
or lower power per unit of performance, or easier power management
optimization, or any combination of the above. Consider ARM machines vs. x86.
It's not so much that ARM machines go faster but that they do so on a fraction
of the power, and that they require only a small amount of silicon to do so.
One other factor is that RISC machines rely on simple operations carefully
arranged by optimizing compilers (or, in some cases, skillfull programmers). A
multi-step operation can be encoded in a sequence of RISC operations run
through an optimizing scheduler more effectively than the equivalent sequence
of steps inside the micro-engine of a CISC processor.
paul
