On 6/13/24 09:33, Adrian Godwin via cctalk wrote:
I may be wrong, but wasn't that a feature of early RISC, possibly the Sparc ? You were compiling to microcode rather than CISC assembler, so you got to think about pipelining in the instruction stream. Just about feasible in assembler but perfectly sensible if the compiler was doing the work.
That sounds a lot like early MIPS processors, where you (or the compiler) had to schedule load and store delay slots as necessary. It made sense, given that the whole premise was to make the silicon simple by having the compiler do all of the bookkeeping.
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