> On Jul 5, 2025, at 8:55 PM, ben via cctalk <[email protected]> wrote:
>
> On 2025-07-05 1:34 p.m., Paul Koning via cctalk wrote:
>>> ...
>> Compared to CDC 6000 mainframes, the 780 (and other DEC computers) are
>> marvels of simplicity. Consider the 6600: 15 chassis each with 750-ish
>> module slots, each with 28 signal pins. A bunch of slots were filled
>> instead by memory modules (5 slots wide), but still you're looking at maybe
>> 5000 wires (or rather, twisted pairs) per chassis, plus 30 or so cable
>> assemblies each with 19 coax inside, to run signals from one chassis to
>> another (or to I/O devices). I assume those were all done by hand; it's not
>> obvious how a robot could do that in the early 1960s, unlike wire wrap
>> backplanes.
>
> And all the wires tuned to have the same delay I bet.
>
>> paul
> Ben.
No, and in fact some of the details are maddening.
Many of the wires are fairly short, a natural length for the distance between
modules. But a non-trivial fraction is significantly longer, and some of the
time it's possible to look at the circuit details and figure out why. But not
always.
An extreme example is the master clock oscillator in 6600 serial number 1
through 7: that is a ring oscillator, with 96 inch interconnecting wires to
provide the correct delay between the phases (25 ns, the sum of wire and
circuit delays). But there are plenty of other places where "odd" wire lengths
appear. In attempting to create a working gate level VHDL model of the 6600 I
chose to model the delay of "long" wires, while ignoring the delay of short
wires. That works reasonably well. Replacing the clock distribution tree by a
behavioral model of a multiphase clock (using the clock offsets shown in the
block diagrams) helps some more and also speeds up the simulation. But it
doesn't completely work even so. It doesn't help that the block diagrams and
the wire lists sometimes disagree about the clock phase. And it's really crazy
to be confronted with an R/S flipflop where the R and S signals are both
asserted simultaneously, with pulses that exactly match if I do what the
diagrams say. Obviously that's not correct, but what would be correct and how
to achieve it is far from clear.
BTW, the 6600 is usually described as having a 100 ns clock. Some more digging
shows a four-phase clock, i.e., with edges offset by 25 ns. That is how much
of the machine is clocked. But the guts of the CPU has what amounts to a 20
phase clock, with clock positions specified as multiples of 5 ns. Not every
phase is used but a surprising number of them is, and it matters -- you don't
stand a chance emulating the CPU's instruction scheduling logic with just four
clock phases,
paul
