SjoerdMeijer added inline comments.
================ Comment at: llvm/lib/Target/AArch64/AArch64InstrInfo.td:720 def FJCVTZS : BaseFPToIntegerUnscaled<0b01, 0b11, 0b110, FPR64, GPR32, - "fjcvtzs", []> { + "fjcvtzs", [(set GPR32:$Rd, (int_aarch64_fjcvtzs FPR64:$Rn))]> { let Inst{31} = 0; ---------------- and a last nit: this needs some reformatting (exceeding the max column width) Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D64495/new/ https://reviews.llvm.org/D64495 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits