[PATCH] D71062: [ARM][MVE] Add vector reduction intrinsics with two vector operands

[Mark Murray via Phabricator via cfe-commits]

MarkMurrayARM added inline comments.


================
Comment at: clang/include/clang/Basic/arm_mve_defs.td:448
+// for example (u32 x) where x is 0 is transformed into (u32 { 0 }) by the
+// Tablegen parser.
+def V {
----------------
See D71066; I just used the numbers bare, so 0 or 1 not (u32 0) or (u32 1).


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D71062/new/

https://reviews.llvm.org/D71062



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