craig.topper added inline comments.
================ Comment at: llvm/lib/Target/X86/X86ISelLowering.cpp:31080 + + BuildMI(blockMBB, DL, TII->get(IsLP64 ? X86::SUB64ri32 : X86::SUB32ri), + physSPReg) ---------------- serge-sans-paille wrote: > craig.topper wrote: > > This uses physSPReg, but doesn't match the condition for when physSPReg is > > a 64-bit register. Same at several places below. > Sorry, I don't understand your remark. Can you elaborate? If physSPReg is RSP then you need to use SUB64ri32 and if its ESP you need to use SUB32ri. The condition you're using here is "IsLP64", but the condition for phySPReg to be RSP is "IsLP64 || Subtarget.isTargetNaCl64()". So there's a mismatch when IsLP64 is false and Subtarget.isTargetNaCl64() is true. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D68720/new/ https://reviews.llvm.org/D68720 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
