Author: Mikhail Maltsev Date: 2020-03-27T16:05:18Z New Revision: bd722ef63f18ee672d60358113431f9bb5c55380
URL: https://github.com/llvm/llvm-project/commit/bd722ef63f18ee672d60358113431f9bb5c55380 DIFF: https://github.com/llvm/llvm-project/commit/bd722ef63f18ee672d60358113431f9bb5c55380.diff LOG: [ARM,CDE] Improve CDE intrinsics testing Summary: This patch: * adds tests for vreinterpret intinsics in big-endian mode * adds C++ runs to the CDE+MVE header compatibility test Reviewers: simon_tatham, MarkMurrayARM, ostannard, dmgreen Reviewed By: simon_tatham Subscribers: kristof.beyls, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D76927 Added: Modified: clang/test/CodeGen/arm-cde-reinterpret.c clang/test/Headers/arm-cde-header.c Removed: ################################################################################ diff --git a/clang/test/CodeGen/arm-cde-reinterpret.c b/clang/test/CodeGen/arm-cde-reinterpret.c index 569b51bdfdbe..c169a88bc4e3 100644 --- a/clang/test/CodeGen/arm-cde-reinterpret.c +++ b/clang/test/CodeGen/arm-cde-reinterpret.c @@ -1,8 +1,11 @@ -// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi \ // RUN: -target-feature +cdecp0 -target-feature +mve.fp \ // RUN: -mfloat-abi hard -O0 -disable-O0-optnone \ -// RUN: -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s --check-prefixes=CHECK,CHECK-LE +// RUN: %clang_cc1 -triple thumbebv8.1m.main-arm-none-eabi \ +// RUN: -target-feature +cdecp0 -target-feature +mve.fp \ +// RUN: -mfloat-abi hard -O0 -disable-O0-optnone \ +// RUN: -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s --check-prefixes=CHECK,CHECK-BE #include <arm_cde.h> @@ -16,7 +19,8 @@ int8x16_t test_s8(uint8x16_t x) { // CHECK-LABEL: @test_u16( // CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <16 x i8> [[X:%.*]] to <8 x i16> +// CHECK-LE-NEXT: [[TMP0:%.*]] = bitcast <16 x i8> [[X:%.*]] to <8 x i16> +// CHECK-BE-NEXT: [[TMP0:%.*]] = call <8 x i16> @llvm.arm.mve.vreinterpretq.v8i16.v16i8(<16 x i8> [[X:%.*]]) // CHECK-NEXT: ret <8 x i16> [[TMP0]] // uint16x8_t test_u16(uint8x16_t x) { @@ -25,7 +29,8 @@ uint16x8_t test_u16(uint8x16_t x) { // CHECK-LABEL: @test_s32( // CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <16 x i8> [[X:%.*]] to <4 x i32> +// CHECK-LE-NEXT: [[TMP0:%.*]] = bitcast <16 x i8> [[X:%.*]] to <4 x i32> +// CHECK-BE-NEXT: [[TMP0:%.*]] = call <4 x i32> @llvm.arm.mve.vreinterpretq.v4i32.v16i8(<16 x i8> [[X:%.*]]) // CHECK-NEXT: ret <4 x i32> [[TMP0]] // int32x4_t test_s32(uint8x16_t x) { @@ -34,7 +39,8 @@ int32x4_t test_s32(uint8x16_t x) { // CHECK-LABEL: @test_u32( // CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <16 x i8> [[X:%.*]] to <4 x i32> +// CHECK-LE-NEXT: [[TMP0:%.*]] = bitcast <16 x i8> [[X:%.*]] to <4 x i32> +// CHECK-BE-NEXT: [[TMP0:%.*]] = call <4 x i32> @llvm.arm.mve.vreinterpretq.v4i32.v16i8(<16 x i8> [[X:%.*]]) // CHECK-NEXT: ret <4 x i32> [[TMP0]] // uint32x4_t test_u32(uint8x16_t x) { @@ -43,7 +49,8 @@ uint32x4_t test_u32(uint8x16_t x) { // CHECK-LABEL: @test_s64( // CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <16 x i8> [[X:%.*]] to <2 x i64> +// CHECK-LE-NEXT: [[TMP0:%.*]] = bitcast <16 x i8> [[X:%.*]] to <2 x i64> +// CHECK-BE-NEXT: [[TMP0:%.*]] = call <2 x i64> @llvm.arm.mve.vreinterpretq.v2i64.v16i8(<16 x i8> [[X:%.*]]) // CHECK-NEXT: ret <2 x i64> [[TMP0]] // int64x2_t test_s64(uint8x16_t x) { @@ -52,7 +59,8 @@ int64x2_t test_s64(uint8x16_t x) { // CHECK-LABEL: @test_u64( // CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <16 x i8> [[X:%.*]] to <2 x i64> +// CHECK-LE-NEXT: [[TMP0:%.*]] = bitcast <16 x i8> [[X:%.*]] to <2 x i64> +// CHECK-BE-NEXT: [[TMP0:%.*]] = call <2 x i64> @llvm.arm.mve.vreinterpretq.v2i64.v16i8(<16 x i8> [[X:%.*]]) // CHECK-NEXT: ret <2 x i64> [[TMP0]] // uint64x2_t test_u64(uint8x16_t x) { @@ -61,7 +69,8 @@ uint64x2_t test_u64(uint8x16_t x) { // CHECK-LABEL: @test_f16( // CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <16 x i8> [[X:%.*]] to <8 x half> +// CHECK-LE-NEXT: [[TMP0:%.*]] = bitcast <16 x i8> [[X:%.*]] to <8 x half> +// CHECK-BE-NEXT: [[TMP0:%.*]] = call <8 x half> @llvm.arm.mve.vreinterpretq.v8f16.v16i8(<16 x i8> [[X:%.*]]) // CHECK-NEXT: ret <8 x half> [[TMP0]] // float16x8_t test_f16(uint8x16_t x) { @@ -70,7 +79,8 @@ float16x8_t test_f16(uint8x16_t x) { // CHECK-LABEL: @test_f32( // CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <16 x i8> [[X:%.*]] to <4 x float> +// CHECK-LE-NEXT: [[TMP0:%.*]] = bitcast <16 x i8> [[X:%.*]] to <4 x float> +// CHECK-BE-NEXT: [[TMP0:%.*]] = call <4 x float> @llvm.arm.mve.vreinterpretq.v4f32.v16i8(<16 x i8> [[X:%.*]]) // CHECK-NEXT: ret <4 x float> [[TMP0]] // float32x4_t test_f32(uint8x16_t x) { diff --git a/clang/test/Headers/arm-cde-header.c b/clang/test/Headers/arm-cde-header.c index e9ff64905162..b2f721a6ff9c 100644 --- a/clang/test/Headers/arm-cde-header.c +++ b/clang/test/Headers/arm-cde-header.c @@ -1,7 +1,9 @@ // RUN: %clang_cc1 -std=c89 -triple thumbv8.1m.main-arm-none-eabi -fallow-half-arguments-and-returns -target-feature +mve.fp -target-feature +cdecp0 -fsyntax-only %s -// RUN: %clang_cc1 -std=c99 -triple thumbv8.1m.main-arm-none-eabi -fallow-half-arguments-and-returns -target-feature +mve.fp -target-feature +cdecp0 -fsyntax-only %s -// RUN: %clang_cc1 -std=c11 -triple thumbv8.1m.main-arm-none-eabi -fallow-half-arguments-and-returns -target-feature +mve.fp -target-feature +cdecp0 -fsyntax-only %s +// RUN: %clang_cc1 -std=c17 -triple thumbv8.1m.main-arm-none-eabi -fallow-half-arguments-and-returns -target-feature +mve -target-feature +cdecp0 -fsyntax-only %s // RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -fallow-half-arguments-and-returns -target-feature +mve.fp -target-feature +cdecp0 -fsyntax-only %s +// RUN: %clang_cc1 -xc++ -std=c++98 -triple thumbv8.1m.main-arm-none-eabi -fallow-half-arguments-and-returns -target-feature +mve -target-feature +cdecp0 -fsyntax-only %s +// RUN: %clang_cc1 -xc++ -std=c++20 -triple thumbv8.1m.main-arm-none-eabi -fallow-half-arguments-and-returns -target-feature +mve.fp -target-feature +cdecp0 -fsyntax-only %s +// RUN: %clang_cc1 -xc++ -triple thumbv8.1m.main-arm-none-eabi -fallow-half-arguments-and-returns -target-feature +mve.fp -target-feature +cdecp0 -fsyntax-only %s // Check that the headers don't conflict with each other #include <arm_cde.h> _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits