jasonliu created this revision.
jasonliu added reviewers: sfertile, nemanjai, hubert.reinterpretcast,
cebowleratibm.
Herald added subscribers: steven.zhang, shchenz.
jasonliu added a reviewer: PowerPC.
jasonliu added a comment.
To reviewers:
Although the patch is showing changes on various ABIInfo classes. But those
classes are actually untouched.
This patch only touches PowerPC TargetCodeGenInfo related classes.
There is little differences across all power pc related target for
TargetCodeGenInfo implementation.
The biggest difference is the different ABIInfo classes it takes.
But we don't necessarily need so many TargetCodeGenInfo for different PowerPC
architect.
So it might be beneficial to common them up as one PPCTargetCodeGenInfo.
https://reviews.llvm.org/D78506
Files:
clang/lib/CodeGen/TargetInfo.cpp
Index: clang/lib/CodeGen/TargetInfo.cpp
===================================================================
--- clang/lib/CodeGen/TargetInfo.cpp
+++ clang/lib/CodeGen/TargetInfo.cpp
@@ -4172,8 +4172,9 @@
/*allowHigherAlign*/ false);
}
-// PowerPC-32
+// PowerPC
namespace {
+// PowerPC-32
/// PPC32_SVR4_ABIInfo - The 32-bit PowerPC ELF (SVR4) ABI information.
class PPC32_SVR4_ABIInfo : public DefaultABIInfo {
bool IsSoftFloatABI;
@@ -4188,10 +4189,136 @@
QualType Ty) const override;
};
-class PPC32TargetCodeGenInfo : public TargetCodeGenInfo {
+// PowerPC-64
+/// PPC64_SVR4_ABIInfo - The 64-bit PowerPC ELF (SVR4) ABI information.
+class PPC64_SVR4_ABIInfo : public SwiftABIInfo {
+public:
+ enum ABIKind {
+ ELFv1 = 0,
+ ELFv2
+ };
+
+private:
+ static const unsigned GPRBits = 64;
+ ABIKind Kind;
+ bool HasQPX;
+ bool IsSoftFloatABI;
+
+ // A vector of float or double will be promoted to <4 x f32> or <4 x f64> and
+ // will be passed in a QPX register.
+ bool IsQPXVectorTy(const Type *Ty) const {
+ if (!HasQPX)
+ return false;
+
+ if (const VectorType *VT = Ty->getAs<VectorType>()) {
+ unsigned NumElements = VT->getNumElements();
+ if (NumElements == 1)
+ return false;
+
+ if (VT->getElementType()->isSpecificBuiltinType(BuiltinType::Double)) {
+ if (getContext().getTypeSize(Ty) <= 256)
+ return true;
+ } else if (VT->getElementType()->
+ isSpecificBuiltinType(BuiltinType::Float)) {
+ if (getContext().getTypeSize(Ty) <= 128)
+ return true;
+ }
+ }
+
+ return false;
+ }
+
+ bool IsQPXVectorTy(QualType Ty) const {
+ return IsQPXVectorTy(Ty.getTypePtr());
+ }
+
+public:
+ PPC64_SVR4_ABIInfo(CodeGen::CodeGenTypes &CGT, ABIKind Kind, bool HasQPX,
+ bool SoftFloatABI)
+ : SwiftABIInfo(CGT), Kind(Kind), HasQPX(HasQPX),
+ IsSoftFloatABI(SoftFloatABI) {}
+
+ bool isPromotableTypeForABI(QualType Ty) const;
+ CharUnits getParamTypeAlignment(QualType Ty) const;
+
+ ABIArgInfo classifyReturnType(QualType RetTy) const;
+ ABIArgInfo classifyArgumentType(QualType Ty) const;
+
+ bool isHomogeneousAggregateBaseType(QualType Ty) const override;
+ bool isHomogeneousAggregateSmallEnough(const Type *Ty,
+ uint64_t Members) const override;
+
+ // TODO: We can add more logic to computeInfo to improve performance.
+ // Example: For aggregate arguments that fit in a register, we could
+ // use getDirectInReg (as is done below for structs containing a single
+ // floating-point value) to avoid pushing them to memory on function
+ // entry. This would require changing the logic in PPCISelLowering
+ // when lowering the parameters in the caller and args in the callee.
+ void computeInfo(CGFunctionInfo &FI) const override {
+ if (!getCXXABI().classifyReturnType(FI))
+ FI.getReturnInfo() = classifyReturnType(FI.getReturnType());
+ for (auto &I : FI.arguments()) {
+ // We rely on the default argument classification for the most part.
+ // One exception: An aggregate containing a single floating-point
+ // or vector item must be passed in a register if one is available.
+ const Type *T = isSingleElementStruct(I.type, getContext());
+ if (T) {
+ const BuiltinType *BT = T->getAs<BuiltinType>();
+ if (IsQPXVectorTy(T) ||
+ (T->isVectorType() && getContext().getTypeSize(T) == 128) ||
+ (BT && BT->isFloatingPoint())) {
+ QualType QT(T, 0);
+ I.info = ABIArgInfo::getDirectInReg(CGT.ConvertType(QT));
+ continue;
+ }
+ }
+ I.info = classifyArgumentType(I.type);
+ }
+ }
+
+ Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
+ QualType Ty) const override;
+
+ bool shouldPassIndirectlyForSwift(ArrayRef<llvm::Type*> scalars,
+ bool asReturnValue) const override {
+ return occupiesMoreThan(CGT, scalars, /*total*/ 4);
+ }
+
+ bool isSwiftErrorInRegister() const override {
+ return false;
+ }
+};
+
+class PPCTargetCodeGenInfo : public TargetCodeGenInfo {
public:
- PPC32TargetCodeGenInfo(CodeGenTypes &CGT, bool SoftFloatABI)
- : TargetCodeGenInfo(new PPC32_SVR4_ABIInfo(CGT, SoftFloatABI)) {}
+ PPCTargetCodeGenInfo(CodeGenTypes &CGT, bool SoftFloatABI) {
+ const TargetInfo &Target = CGT.getTarget();
+ const llvm::Triple &Triple = Target.getTriple();
+ const llvm::Triple::ArchType &Arch = Triple.getArch();
+ if (Arch == llvm::Triple::ppc) {
+ is64Bit = false;
+ TargetCodeGenInfo(new PPC32_SVR4_ABIInfo(
+ CGT, SoftFloatABI || Target.hasFeature("spe")));
+ return;
+ }
+
+ if (!Triple.isOSBinFormatELF()) {
+ assert(Arch != llvm::Triple::ppc64le && "PPC64 LE non-ELF not supported!");
+ TargetCodeGenInfo(new DefaultABIInfo(CGT));
+ return;
+ }
+
+ bool HasQPX = Target.getABI() == "elfv1-qpx";
+ PPC64_SVR4_ABIInfo::ABIKind Kind;
+ if (Arch == llvm::Triple::ppc64)
+ Kind = Target.getABI() == "elfv2" ? PPC64_SVR4_ABIInfo::ELFv2
+ : PPC64_SVR4_ABIInfo::ELFv1;
+ else if (Arch == llvm::Triple::ppc64le)
+ Kind = (Target.getABI() == "elfv1" || HasQPX) ? PPC64_SVR4_ABIInfo::ELFv1
+ : PPC64_SVR4_ABIInfo::ELFv2;
+ TargetCodeGenInfo(new PPC64_SVR4_ABIInfo(CGT, Kind, HasQPX, SoftFloatABI));
+ return;
+ }
int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
// This is recovered from gcc output.
@@ -4200,9 +4327,62 @@
bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
llvm::Value *Address) const override;
+
+private:
+ bool is64Bit = true;
};
}
+bool PPCTargetCodeGenInfo::initDwarfEHRegSizeTable(
+ CodeGen::CodeGenFunction &CGF, llvm::Value *Address) const {
+ // This is calculated from the LLVM and GCC tables and verified
+ // against gcc output. AFAIK all ABIs use the same encoding.
+
+ CodeGen::CGBuilderTy &Builder = CGF.Builder;
+
+ llvm::IntegerType *i8 = CGF.Int8Ty;
+ llvm::Value *Four8 = llvm::ConstantInt::get(i8, 4);
+ llvm::Value *Eight8 = llvm::ConstantInt::get(i8, 8);
+ llvm::Value *Sixteen8 = llvm::ConstantInt::get(i8, 16);
+
+ // 0-31: r0-31, the 4-byte or 8-byte general-purpose registers
+ AssignToArrayRange(Builder, Address, is64Bit ? Eight8 : Four8, 0, 31);
+
+ // 32-63: fp0-31, the 8-byte floating-point registers
+ AssignToArrayRange(Builder, Address, Eight8, 32, 63);
+
+ // 64-76 are various 4-byte or 8-byte special-purpose registers:
+ // 64: mq
+ // 65: lr
+ // 66: ctr
+ // 67: ap
+ AssignToArrayRange(Builder, Address, is64Bit ? Eight8 : Four8, 64, 67);
+
+ // 68-76 are various 4-byte special-purpose registers:
+ // 68-75 cr0-7
+ // 76: xer
+ AssignToArrayRange(Builder, Address, Four8, 68, 76);
+
+ // 77-108: v0-31, the 16-byte vector registers
+ AssignToArrayRange(Builder, Address, Sixteen8, 77, 108);
+
+ // 109: vrsave
+ // 110: vscr
+ // 111: spe_acc
+ // 112: spefscr
+ // 113: sfp
+ AssignToArrayRange(Builder, Address, is64Bit ? Eight8 : Four8, 109, 113);
+
+ // 64-bit only registers:
+ // 114: tfhar
+ // 115: tfiar
+ // 116: texasr
+ if (is64Bit)
+ AssignToArrayRange(Builder, Address, Eight8, 109, 116);
+
+ return false;
+}
+
CharUnits PPC32_SVR4_ABIInfo::getParamTypeAlignment(QualType Ty) const {
// Complex types are passed just like their elements
if (const ComplexType *CTy = Ty->getAs<ComplexType>())
@@ -4382,182 +4562,6 @@
return Result;
}
-bool
-PPC32TargetCodeGenInfo::initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
- llvm::Value *Address) const {
- // This is calculated from the LLVM and GCC tables and verified
- // against gcc output. AFAIK all ABIs use the same encoding.
-
- CodeGen::CGBuilderTy &Builder = CGF.Builder;
-
- llvm::IntegerType *i8 = CGF.Int8Ty;
- llvm::Value *Four8 = llvm::ConstantInt::get(i8, 4);
- llvm::Value *Eight8 = llvm::ConstantInt::get(i8, 8);
- llvm::Value *Sixteen8 = llvm::ConstantInt::get(i8, 16);
-
- // 0-31: r0-31, the 4-byte general-purpose registers
- AssignToArrayRange(Builder, Address, Four8, 0, 31);
-
- // 32-63: fp0-31, the 8-byte floating-point registers
- AssignToArrayRange(Builder, Address, Eight8, 32, 63);
-
- // 64-76 are various 4-byte special-purpose registers:
- // 64: mq
- // 65: lr
- // 66: ctr
- // 67: ap
- // 68-75 cr0-7
- // 76: xer
- AssignToArrayRange(Builder, Address, Four8, 64, 76);
-
- // 77-108: v0-31, the 16-byte vector registers
- AssignToArrayRange(Builder, Address, Sixteen8, 77, 108);
-
- // 109: vrsave
- // 110: vscr
- // 111: spe_acc
- // 112: spefscr
- // 113: sfp
- AssignToArrayRange(Builder, Address, Four8, 109, 113);
-
- return false;
-}
-
-// PowerPC-64
-
-namespace {
-/// PPC64_SVR4_ABIInfo - The 64-bit PowerPC ELF (SVR4) ABI information.
-class PPC64_SVR4_ABIInfo : public SwiftABIInfo {
-public:
- enum ABIKind {
- ELFv1 = 0,
- ELFv2
- };
-
-private:
- static const unsigned GPRBits = 64;
- ABIKind Kind;
- bool HasQPX;
- bool IsSoftFloatABI;
-
- // A vector of float or double will be promoted to <4 x f32> or <4 x f64> and
- // will be passed in a QPX register.
- bool IsQPXVectorTy(const Type *Ty) const {
- if (!HasQPX)
- return false;
-
- if (const VectorType *VT = Ty->getAs<VectorType>()) {
- unsigned NumElements = VT->getNumElements();
- if (NumElements == 1)
- return false;
-
- if (VT->getElementType()->isSpecificBuiltinType(BuiltinType::Double)) {
- if (getContext().getTypeSize(Ty) <= 256)
- return true;
- } else if (VT->getElementType()->
- isSpecificBuiltinType(BuiltinType::Float)) {
- if (getContext().getTypeSize(Ty) <= 128)
- return true;
- }
- }
-
- return false;
- }
-
- bool IsQPXVectorTy(QualType Ty) const {
- return IsQPXVectorTy(Ty.getTypePtr());
- }
-
-public:
- PPC64_SVR4_ABIInfo(CodeGen::CodeGenTypes &CGT, ABIKind Kind, bool HasQPX,
- bool SoftFloatABI)
- : SwiftABIInfo(CGT), Kind(Kind), HasQPX(HasQPX),
- IsSoftFloatABI(SoftFloatABI) {}
-
- bool isPromotableTypeForABI(QualType Ty) const;
- CharUnits getParamTypeAlignment(QualType Ty) const;
-
- ABIArgInfo classifyReturnType(QualType RetTy) const;
- ABIArgInfo classifyArgumentType(QualType Ty) const;
-
- bool isHomogeneousAggregateBaseType(QualType Ty) const override;
- bool isHomogeneousAggregateSmallEnough(const Type *Ty,
- uint64_t Members) const override;
-
- // TODO: We can add more logic to computeInfo to improve performance.
- // Example: For aggregate arguments that fit in a register, we could
- // use getDirectInReg (as is done below for structs containing a single
- // floating-point value) to avoid pushing them to memory on function
- // entry. This would require changing the logic in PPCISelLowering
- // when lowering the parameters in the caller and args in the callee.
- void computeInfo(CGFunctionInfo &FI) const override {
- if (!getCXXABI().classifyReturnType(FI))
- FI.getReturnInfo() = classifyReturnType(FI.getReturnType());
- for (auto &I : FI.arguments()) {
- // We rely on the default argument classification for the most part.
- // One exception: An aggregate containing a single floating-point
- // or vector item must be passed in a register if one is available.
- const Type *T = isSingleElementStruct(I.type, getContext());
- if (T) {
- const BuiltinType *BT = T->getAs<BuiltinType>();
- if (IsQPXVectorTy(T) ||
- (T->isVectorType() && getContext().getTypeSize(T) == 128) ||
- (BT && BT->isFloatingPoint())) {
- QualType QT(T, 0);
- I.info = ABIArgInfo::getDirectInReg(CGT.ConvertType(QT));
- continue;
- }
- }
- I.info = classifyArgumentType(I.type);
- }
- }
-
- Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
- QualType Ty) const override;
-
- bool shouldPassIndirectlyForSwift(ArrayRef<llvm::Type*> scalars,
- bool asReturnValue) const override {
- return occupiesMoreThan(CGT, scalars, /*total*/ 4);
- }
-
- bool isSwiftErrorInRegister() const override {
- return false;
- }
-};
-
-class PPC64_SVR4_TargetCodeGenInfo : public TargetCodeGenInfo {
-
-public:
- PPC64_SVR4_TargetCodeGenInfo(CodeGenTypes &CGT,
- PPC64_SVR4_ABIInfo::ABIKind Kind, bool HasQPX,
- bool SoftFloatABI)
- : TargetCodeGenInfo(new PPC64_SVR4_ABIInfo(CGT, Kind, HasQPX,
- SoftFloatABI)) {}
-
- int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
- // This is recovered from gcc output.
- return 1; // r1 is the dedicated stack pointer
- }
-
- bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
- llvm::Value *Address) const override;
-};
-
-class PPC64TargetCodeGenInfo : public DefaultTargetCodeGenInfo {
-public:
- PPC64TargetCodeGenInfo(CodeGenTypes &CGT) : DefaultTargetCodeGenInfo(CGT) {}
-
- int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
- // This is recovered from gcc output.
- return 1; // r1 is the dedicated stack pointer
- }
-
- bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
- llvm::Value *Address) const override;
-};
-
-}
-
// Return true if the ABI requires Ty to be passed sign- or zero-
// extended to 64 bits.
bool
@@ -4955,68 +4959,6 @@
TypeInfo, SlotSize, /*AllowHigher*/ true);
}
-static bool
-PPC64_initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
- llvm::Value *Address) {
- // This is calculated from the LLVM and GCC tables and verified
- // against gcc output. AFAIK all ABIs use the same encoding.
-
- CodeGen::CGBuilderTy &Builder = CGF.Builder;
-
- llvm::IntegerType *i8 = CGF.Int8Ty;
- llvm::Value *Four8 = llvm::ConstantInt::get(i8, 4);
- llvm::Value *Eight8 = llvm::ConstantInt::get(i8, 8);
- llvm::Value *Sixteen8 = llvm::ConstantInt::get(i8, 16);
-
- // 0-31: r0-31, the 8-byte general-purpose registers
- AssignToArrayRange(Builder, Address, Eight8, 0, 31);
-
- // 32-63: fp0-31, the 8-byte floating-point registers
- AssignToArrayRange(Builder, Address, Eight8, 32, 63);
-
- // 64-67 are various 8-byte special-purpose registers:
- // 64: mq
- // 65: lr
- // 66: ctr
- // 67: ap
- AssignToArrayRange(Builder, Address, Eight8, 64, 67);
-
- // 68-76 are various 4-byte special-purpose registers:
- // 68-75 cr0-7
- // 76: xer
- AssignToArrayRange(Builder, Address, Four8, 68, 76);
-
- // 77-108: v0-31, the 16-byte vector registers
- AssignToArrayRange(Builder, Address, Sixteen8, 77, 108);
-
- // 109: vrsave
- // 110: vscr
- // 111: spe_acc
- // 112: spefscr
- // 113: sfp
- // 114: tfhar
- // 115: tfiar
- // 116: texasr
- AssignToArrayRange(Builder, Address, Eight8, 109, 116);
-
- return false;
-}
-
-bool
-PPC64_SVR4_TargetCodeGenInfo::initDwarfEHRegSizeTable(
- CodeGen::CodeGenFunction &CGF,
- llvm::Value *Address) const {
-
- return PPC64_initDwarfEHRegSizeTable(CGF, Address);
-}
-
-bool
-PPC64TargetCodeGenInfo::initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
- llvm::Value *Address) const {
-
- return PPC64_initDwarfEHRegSizeTable(CGF, Address);
-}
-
//===----------------------------------------------------------------------===//
// AArch64 ABI Implementation
//===----------------------------------------------------------------------===//
@@ -10263,34 +10205,11 @@
return SetCGInfo(new ARMTargetCodeGenInfo(Types, Kind));
}
-
case llvm::Triple::ppc:
- return SetCGInfo(
- new PPC32TargetCodeGenInfo(Types, CodeGenOpts.FloatABI == "soft" ||
- getTarget().hasFeature("spe")));
case llvm::Triple::ppc64:
- if (Triple.isOSBinFormatELF()) {
- PPC64_SVR4_ABIInfo::ABIKind Kind = PPC64_SVR4_ABIInfo::ELFv1;
- if (getTarget().getABI() == "elfv2")
- Kind = PPC64_SVR4_ABIInfo::ELFv2;
- bool HasQPX = getTarget().getABI() == "elfv1-qpx";
- bool IsSoftFloat = CodeGenOpts.FloatABI == "soft";
-
- return SetCGInfo(new PPC64_SVR4_TargetCodeGenInfo(Types, Kind, HasQPX,
- IsSoftFloat));
- } else
- return SetCGInfo(new PPC64TargetCodeGenInfo(Types));
- case llvm::Triple::ppc64le: {
- assert(Triple.isOSBinFormatELF() && "PPC64 LE non-ELF not supported!");
- PPC64_SVR4_ABIInfo::ABIKind Kind = PPC64_SVR4_ABIInfo::ELFv2;
- if (getTarget().getABI() == "elfv1" || getTarget().getABI() == "elfv1-qpx")
- Kind = PPC64_SVR4_ABIInfo::ELFv1;
- bool HasQPX = getTarget().getABI() == "elfv1-qpx";
- bool IsSoftFloat = CodeGenOpts.FloatABI == "soft";
-
- return SetCGInfo(new PPC64_SVR4_TargetCodeGenInfo(Types, Kind, HasQPX,
- IsSoftFloat));
- }
+ case llvm::Triple::ppc64le:
+ return SetCGInfo(
+ new PPCTargetCodeGenInfo(Types, CodeGenOpts.FloatABI == "soft"));
case llvm::Triple::nvptx:
case llvm::Triple::nvptx64:
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