regehr added a comment.
> Did you mean to check something like the following?
>
> define i32 @src(i1 %cond, i32 %x) {
> %x2 = freeze i32 %x
> %s = select i1 %cond, i32 %x2, i32 undef
> ret i32 %s
> }
>
> define i32 @tgt(i1 %cond, i32 %x) {
> %x2 = freeze i32 %x
> ret i32 %x2
> }
that's fine but I still don't understand why the counterexample to my version
says %x2 in @src can be undef
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D83360/new/
https://reviews.llvm.org/D83360
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