[PATCH] D71760: [POC][SVE] Allow code generation for fixed length vectorised loops [Patch 1/2].

[Paul Walker via Phabricator via cfe-commits]

paulwalker-arm updated this revision to Diff 277452.
paulwalker-arm removed reviewers: rengolin, efriedma.
paulwalker-arm added a subscriber: efriedma.
paulwalker-arm added a comment.
Herald added a reviewer: rengolin.
Herald added a reviewer: efriedma.
Herald added subscribers: cfe-commits, dang.
Herald added a project: clang.

Rebasing to reflect the majority of the functionality is now in master.  What 
remains is likely to be abandoned in favour of function attributes but it's 
here for those who want to experiment.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D71760/new/

https://reviews.llvm.org/D71760

Files:
  clang/include/clang/Driver/Options.td
  clang/lib/Driver/ToolChains/Clang.cpp
  llvm/lib/Target/AArch64/AArch64FrameLowering.cpp


Index: llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
===================================================================
--- llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
+++ llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
@@ -1819,7 +1819,7 @@
         if (FPOffsetFits && CanUseBP) // Both are ok. Pick the best.
           UseFP = PreferFP;
         else if (!CanUseBP) { // Can't use BP. Forced to use FP.
-          assert(!SVEStackSize && "Expected BP to be available");
+          // assert(!SVEStackSize && "Expected BP to be available");
           UseFP = true;
         }
         // else we can use BP and FP, but the offset from FP won't fit.
Index: clang/lib/Driver/ToolChains/Clang.cpp
===================================================================
--- clang/lib/Driver/ToolChains/Clang.cpp
+++ clang/lib/Driver/ToolChains/Clang.cpp
@@ -1715,6 +1715,22 @@
     if (IndirectBranches)
       CmdArgs.push_back("-mbranch-target-enforce");
   }
+
+  if (any_of(CmdArgs, [](const char *Arg) {
+        return (strcmp(Arg, "+sve") == 0 || strcmp(Arg, "+sve2") == 0);
+      })) {
+    if (Arg *A = Args.getLastArg(options::OPT_msve_vector_bits)) {
+      StringRef Bits = A->getValue();
+      if (Bits != "scalable") {
+        CmdArgs.push_back("-mllvm");
+        CmdArgs.push_back(
+            Args.MakeArgString("-aarch64-sve-vector-bits-min=" + Bits));
+        // CmdArgs.push_back("-mllvm");
+        // CmdArgs.push_back(
+        //    Args.MakeArgString("-aarch64-sve-vector-bits-max=" + Bits));
+      }
+    }
+  }
 }
 
 void Clang::AddMIPSTargetArgs(const ArgList &Args,
Index: clang/include/clang/Driver/Options.td
===================================================================
--- clang/include/clang/Driver/Options.td
+++ clang/include/clang/Driver/Options.td
@@ -2351,6 +2351,10 @@
 
 def mharden_sls_EQ : Joined<["-"], "mharden-sls=">,
   HelpText<"Select straight-line speculation hardening scope">;
+def msve_vector_bits : Joined<["-"], "msve-vector-bits=">,
+  Group<m_aarch64_Features_Group>,
+  HelpText<"Specify the size in bits of an SVE vector register."
+           " Has no effect unless SVE is enabled. (Default is \"scalable\")">;
 
 def msimd128 : Flag<["-"], "msimd128">, Group<m_wasm_Features_Group>;
 def munimplemented_simd128 : Flag<["-"], "munimplemented-simd128">, 
Group<m_wasm_Features_Group>;



Index: llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
===================================================================
--- llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
+++ llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
@@ -1819,7 +1819,7 @@
         if (FPOffsetFits && CanUseBP) // Both are ok. Pick the best.
           UseFP = PreferFP;
         else if (!CanUseBP) { // Can't use BP. Forced to use FP.
-          assert(!SVEStackSize && "Expected BP to be available");
+          // assert(!SVEStackSize && "Expected BP to be available");
           UseFP = true;
         }
         // else we can use BP and FP, but the offset from FP won't fit.
Index: clang/lib/Driver/ToolChains/Clang.cpp
===================================================================
--- clang/lib/Driver/ToolChains/Clang.cpp
+++ clang/lib/Driver/ToolChains/Clang.cpp
@@ -1715,6 +1715,22 @@
     if (IndirectBranches)
       CmdArgs.push_back("-mbranch-target-enforce");
   }
+
+  if (any_of(CmdArgs, [](const char *Arg) {
+        return (strcmp(Arg, "+sve") == 0 || strcmp(Arg, "+sve2") == 0);
+      })) {
+    if (Arg *A = Args.getLastArg(options::OPT_msve_vector_bits)) {
+      StringRef Bits = A->getValue();
+      if (Bits != "scalable") {
+        CmdArgs.push_back("-mllvm");
+        CmdArgs.push_back(
+            Args.MakeArgString("-aarch64-sve-vector-bits-min=" + Bits));
+        // CmdArgs.push_back("-mllvm");
+        // CmdArgs.push_back(
+        //    Args.MakeArgString("-aarch64-sve-vector-bits-max=" + Bits));
+      }
+    }
+  }
 }
 
 void Clang::AddMIPSTargetArgs(const ArgList &Args,
Index: clang/include/clang/Driver/Options.td
===================================================================
--- clang/include/clang/Driver/Options.td
+++ clang/include/clang/Driver/Options.td
@@ -2351,6 +2351,10 @@
 
 def mharden_sls_EQ : Joined<["-"], "mharden-sls=">,
   HelpText<"Select straight-line speculation hardening scope">;
+def msve_vector_bits : Joined<["-"], "msve-vector-bits=">,
+  Group<m_aarch64_Features_Group>,
+  HelpText<"Specify the size in bits of an SVE vector register."
+           " Has no effect unless SVE is enabled. (Default is \"scalable\")">;
 
 def msimd128 : Flag<["-"], "msimd128">, Group<m_wasm_Features_Group>;
 def munimplemented_simd128 : Flag<["-"], "munimplemented-simd128">, Group<m_wasm_Features_Group>;

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