arsenm added inline comments.
================ Comment at: llvm/include/llvm/CodeGen/MachineCfgTraits.h:44 + // use on a 32-bit architecture. + assert(wrapped != (uintptr_t)-1 && wrapped != (uintptr_t)-2); + ---------------- I feel like there should be a better way to do this; we should probably have an assert where virtual registers are created ================ Comment at: llvm/include/llvm/CodeGen/MachineCfgTraits.h:101 + return nullptr; + return m_regInfo->getUniqueVRegDef(value)->getParent(); + } ---------------- I think regular getVRegDef is preferable for SSA MIR Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D83088/new/ https://reviews.llvm.org/D83088 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
