Author: Amy Kwan Date: 2020-07-22T17:58:14-05:00 New Revision: 5f110273954ac152c9690b6cdf2a2e46f8908f0a
URL: https://github.com/llvm/llvm-project/commit/5f110273954ac152c9690b6cdf2a2e46f8908f0a DIFF: https://github.com/llvm/llvm-project/commit/5f110273954ac152c9690b6cdf2a2e46f8908f0a.diff LOG: [PowerPC][Power10] Fix vins*vlx instructions to have i32 arguments. Previously, the vins*vlx instructions were incorrectly defined with i64 as the second argument. This patches fixes this issue by correcting the second argument of the vins*vlx instructions/intrinsics to be i32. Differential Revision: https://reviews.llvm.org/D84277 Added: Modified: clang/include/clang/Basic/BuiltinsPPC.def clang/test/CodeGen/builtins-ppc-p10vector.c llvm/include/llvm/IR/IntrinsicsPowerPC.td llvm/lib/Target/PowerPC/PPCInstrPrefix.td llvm/test/CodeGen/PowerPC/builtins-ppc-p10permute.ll Removed: ################################################################################ diff --git a/clang/include/clang/Basic/BuiltinsPPC.def b/clang/include/clang/Basic/BuiltinsPPC.def index b74cb8df78ba..5aed03f74f65 100644 --- a/clang/include/clang/Basic/BuiltinsPPC.def +++ b/clang/include/clang/Basic/BuiltinsPPC.def @@ -329,12 +329,12 @@ BUILTIN(__builtin_altivec_vinswlx, "V4UiV4UiUiUi", "") BUILTIN(__builtin_altivec_vinswrx, "V4UiV4UiUiUi", "") BUILTIN(__builtin_altivec_vinsdlx, "V2ULLiV2ULLiULLiULLi", "") BUILTIN(__builtin_altivec_vinsdrx, "V2ULLiV2ULLiULLiULLi", "") -BUILTIN(__builtin_altivec_vinsbvlx, "V16UcV16UcULLiV16Uc", "") -BUILTIN(__builtin_altivec_vinsbvrx, "V16UcV16UcULLiV16Uc", "") -BUILTIN(__builtin_altivec_vinshvlx, "V8UsV8UsULLiV8Us", "") -BUILTIN(__builtin_altivec_vinshvrx, "V8UsV8UsULLiV8Us", "") -BUILTIN(__builtin_altivec_vinswvlx, "V4UiV4UiULLiV4Ui", "") -BUILTIN(__builtin_altivec_vinswvrx, "V4UiV4UiULLiV4Ui", "") +BUILTIN(__builtin_altivec_vinsbvlx, "V16UcV16UcUiV16Uc", "") +BUILTIN(__builtin_altivec_vinsbvrx, "V16UcV16UcUiV16Uc", "") +BUILTIN(__builtin_altivec_vinshvlx, "V8UsV8UsUiV8Us", "") +BUILTIN(__builtin_altivec_vinshvrx, "V8UsV8UsUiV8Us", "") +BUILTIN(__builtin_altivec_vinswvlx, "V4UiV4UiUiV4Ui", "") +BUILTIN(__builtin_altivec_vinswvrx, "V4UiV4UiUiV4Ui", "") // VSX built-ins. diff --git a/clang/test/CodeGen/builtins-ppc-p10vector.c b/clang/test/CodeGen/builtins-ppc-p10vector.c index 0d084c6eed85..6f38ac77ee24 100644 --- a/clang/test/CodeGen/builtins-ppc-p10vector.c +++ b/clang/test/CodeGen/builtins-ppc-p10vector.c @@ -434,25 +434,25 @@ vector unsigned long long test_vec_insertl_ul(void) { } vector unsigned char test_vec_insertl_ucv(void) { - // CHECK-BE: @llvm.ppc.altivec.vinsbvlx(<16 x i8> %{{.+}}, i64 %{{.+}}, <16 x i8> + // CHECK-BE: @llvm.ppc.altivec.vinsbvlx(<16 x i8> %{{.+}}, i32 %{{.+}}, <16 x i8> // CHECK-BE-NEXT: ret <16 x i8> - // CHECK-LE: @llvm.ppc.altivec.vinsbvrx(<16 x i8> %{{.+}}, i64 %{{.+}}, <16 x i8> + // CHECK-LE: @llvm.ppc.altivec.vinsbvrx(<16 x i8> %{{.+}}, i32 %{{.+}}, <16 x i8> // CHECK-LE-NEXT: ret <16 x i8> return vec_insertl(vuca, vucb, uia); } vector unsigned short test_vec_insertl_usv(void) { - // CHECK-BE: @llvm.ppc.altivec.vinshvlx(<8 x i16> %{{.+}}, i64 %{{.+}}, <8 x i16> + // CHECK-BE: @llvm.ppc.altivec.vinshvlx(<8 x i16> %{{.+}}, i32 %{{.+}}, <8 x i16> // CHECK-BE-NEXT: ret <8 x i16> - // CHECK-LE: @llvm.ppc.altivec.vinshvrx(<8 x i16> %{{.+}}, i64 %{{.+}}, <8 x i16> + // CHECK-LE: @llvm.ppc.altivec.vinshvrx(<8 x i16> %{{.+}}, i32 %{{.+}}, <8 x i16> // CHECK-LE-NEXT: ret <8 x i16> return vec_insertl(vusa, vusb, uia); } vector unsigned int test_vec_insertl_uiv(void) { - // CHECK-BE: @llvm.ppc.altivec.vinswvlx(<4 x i32> %{{.+}}, i64 %{{.+}}, <4 x i32> + // CHECK-BE: @llvm.ppc.altivec.vinswvlx(<4 x i32> %{{.+}}, i32 %{{.+}}, <4 x i32> // CHECK-BE-NEXT: ret <4 x i32> - // CHECK-LE: @llvm.ppc.altivec.vinswvrx(<4 x i32> %{{.+}}, i64 %{{.+}}, <4 x i32> + // CHECK-LE: @llvm.ppc.altivec.vinswvrx(<4 x i32> %{{.+}}, i32 %{{.+}}, <4 x i32> // CHECK-LE-NEXT: ret <4 x i32> return vec_insertl(vuia, vuib, uia); } @@ -490,25 +490,25 @@ vector unsigned long long test_vec_inserth_ul(void) { } vector unsigned char test_vec_inserth_ucv(void) { - // CHECK-BE: @llvm.ppc.altivec.vinsbvrx(<16 x i8> %{{.+}}, i64 %{{.+}}, <16 x i8> + // CHECK-BE: @llvm.ppc.altivec.vinsbvrx(<16 x i8> %{{.+}}, i32 %{{.+}}, <16 x i8> // CHECK-BE-NEXT: ret <16 x i8> - // CHECK-LE: @llvm.ppc.altivec.vinsbvlx(<16 x i8> %{{.+}}, i64 %{{.+}}, <16 x i8> + // CHECK-LE: @llvm.ppc.altivec.vinsbvlx(<16 x i8> %{{.+}}, i32 %{{.+}}, <16 x i8> // CHECK-LE-NEXT: ret <16 x i8> return vec_inserth(vuca, vucb, uia); } vector unsigned short test_vec_inserth_usv(void) { - // CHECK-BE: @llvm.ppc.altivec.vinshvrx(<8 x i16> %{{.+}}, i64 %{{.+}}, <8 x i16> + // CHECK-BE: @llvm.ppc.altivec.vinshvrx(<8 x i16> %{{.+}}, i32 %{{.+}}, <8 x i16> // CHECK-BE-NEXT: ret <8 x i16> - // CHECK-LE: @llvm.ppc.altivec.vinshvlx(<8 x i16> %{{.+}}, i64 %{{.+}}, <8 x i16> + // CHECK-LE: @llvm.ppc.altivec.vinshvlx(<8 x i16> %{{.+}}, i32 %{{.+}}, <8 x i16> // CHECK-LE-NEXT: ret <8 x i16> return vec_inserth(vusa, vusb, uia); } vector unsigned int test_vec_inserth_uiv(void) { - // CHECK-BE: @llvm.ppc.altivec.vinswvrx(<4 x i32> %{{.+}}, i64 %{{.+}}, <4 x i32> + // CHECK-BE: @llvm.ppc.altivec.vinswvrx(<4 x i32> %{{.+}}, i32 %{{.+}}, <4 x i32> // CHECK-BE-NEXT: ret <4 x i32> - // CHECK-LE: @llvm.ppc.altivec.vinswvlx(<4 x i32> %{{.+}}, i64 %{{.+}}, <4 x i32> + // CHECK-LE: @llvm.ppc.altivec.vinswvlx(<4 x i32> %{{.+}}, i32 %{{.+}}, <4 x i32> // CHECK-LE-NEXT: ret <4 x i32> return vec_inserth(vuia, vuib, uia); } diff --git a/llvm/include/llvm/IR/IntrinsicsPowerPC.td b/llvm/include/llvm/IR/IntrinsicsPowerPC.td index d2d418bc2d64..23bcf3ce1959 100644 --- a/llvm/include/llvm/IR/IntrinsicsPowerPC.td +++ b/llvm/include/llvm/IR/IntrinsicsPowerPC.td @@ -500,27 +500,27 @@ let TargetPrefix = "ppc" in { // All intrinsics start with "llvm.ppc.". [IntrNoMem]>; def int_ppc_altivec_vinsbvlx : GCCBuiltin<"__builtin_altivec_vinsbvlx">, Intrinsic<[llvm_v16i8_ty], - [llvm_v16i8_ty, llvm_i64_ty, llvm_v16i8_ty], + [llvm_v16i8_ty, llvm_i32_ty, llvm_v16i8_ty], [IntrNoMem]>; def int_ppc_altivec_vinsbvrx : GCCBuiltin<"__builtin_altivec_vinsbvrx">, Intrinsic<[llvm_v16i8_ty], - [llvm_v16i8_ty, llvm_i64_ty, llvm_v16i8_ty], + [llvm_v16i8_ty, llvm_i32_ty, llvm_v16i8_ty], [IntrNoMem]>; def int_ppc_altivec_vinshvlx : GCCBuiltin<"__builtin_altivec_vinshvlx">, Intrinsic<[llvm_v8i16_ty], - [llvm_v8i16_ty, llvm_i64_ty, llvm_v8i16_ty], + [llvm_v8i16_ty, llvm_i32_ty, llvm_v8i16_ty], [IntrNoMem]>; def int_ppc_altivec_vinshvrx : GCCBuiltin<"__builtin_altivec_vinshvrx">, Intrinsic<[llvm_v8i16_ty], - [llvm_v8i16_ty, llvm_i64_ty, llvm_v8i16_ty], + [llvm_v8i16_ty, llvm_i32_ty, llvm_v8i16_ty], [IntrNoMem]>; def int_ppc_altivec_vinswvlx : GCCBuiltin<"__builtin_altivec_vinswvlx">, Intrinsic<[llvm_v4i32_ty], - [llvm_v4i32_ty, llvm_i64_ty, llvm_v4i32_ty], + [llvm_v4i32_ty, llvm_i32_ty, llvm_v4i32_ty], [IntrNoMem]>; def int_ppc_altivec_vinswvrx : GCCBuiltin<"__builtin_altivec_vinswvrx">, Intrinsic<[llvm_v4i32_ty], - [llvm_v4i32_ty, llvm_i64_ty, llvm_v4i32_ty], + [llvm_v4i32_ty, llvm_i32_ty, llvm_v4i32_ty], [IntrNoMem]>; // P10 Vector Insert with immediate. def int_ppc_altivec_vinsw : diff --git a/llvm/lib/Target/PowerPC/PPCInstrPrefix.td b/llvm/lib/Target/PowerPC/PPCInstrPrefix.td index 4c9f9e8bb083..832c66158f10 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrPrefix.td +++ b/llvm/lib/Target/PowerPC/PPCInstrPrefix.td @@ -245,7 +245,7 @@ class VXForm_RD5_N3_VB5<bits<11> xo, dag OOL, dag IOL, string asmstr, // VX-Form: [PO VRT RA VRB XO]. // Destructive (insert) forms are suffixed with _ins. class VXForm_VTB5_RA5_ins<bits<11> xo, string opc, list<dag> pattern> - : VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vDi, g8rc:$rA, vrrc:$vB), + : VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vDi, gprc:$rA, vrrc:$vB), !strconcat(opc, " $vD, $rA, $vB"), IIC_VecGeneral, pattern>, RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">; @@ -836,32 +836,32 @@ let Predicates = [IsISA3_1] in { def VINSBVLX : VXForm_VTB5_RA5_ins<15, "vinsbvlx", [(set v16i8:$vD, - (int_ppc_altivec_vinsbvlx v16i8:$vDi, i64:$rA, + (int_ppc_altivec_vinsbvlx v16i8:$vDi, i32:$rA, v16i8:$vB))]>; def VINSBVRX : VXForm_VTB5_RA5_ins<271, "vinsbvrx", [(set v16i8:$vD, - (int_ppc_altivec_vinsbvrx v16i8:$vDi, i64:$rA, + (int_ppc_altivec_vinsbvrx v16i8:$vDi, i32:$rA, v16i8:$vB))]>; def VINSHVLX : VXForm_VTB5_RA5_ins<79, "vinshvlx", [(set v8i16:$vD, - (int_ppc_altivec_vinshvlx v8i16:$vDi, i64:$rA, + (int_ppc_altivec_vinshvlx v8i16:$vDi, i32:$rA, v8i16:$vB))]>; def VINSHVRX : VXForm_VTB5_RA5_ins<335, "vinshvrx", [(set v8i16:$vD, - (int_ppc_altivec_vinshvrx v8i16:$vDi, i64:$rA, + (int_ppc_altivec_vinshvrx v8i16:$vDi, i32:$rA, v8i16:$vB))]>; def VINSWVLX : VXForm_VTB5_RA5_ins<143, "vinswvlx", [(set v4i32:$vD, - (int_ppc_altivec_vinswvlx v4i32:$vDi, i64:$rA, + (int_ppc_altivec_vinswvlx v4i32:$vDi, i32:$rA, v4i32:$vB))]>; def VINSWVRX : VXForm_VTB5_RA5_ins<399, "vinswvrx", [(set v4i32:$vD, - (int_ppc_altivec_vinswvrx v4i32:$vDi, i64:$rA, + (int_ppc_altivec_vinswvrx v4i32:$vDi, i32:$rA, v4i32:$vB))]>; def VINSBLX : VXForm_VRT5_RAB5_ins<527, "vinsblx", diff --git a/llvm/test/CodeGen/PowerPC/builtins-ppc-p10permute.ll b/llvm/test/CodeGen/PowerPC/builtins-ppc-p10permute.ll index 3e4a509dc943..73a174297cac 100644 --- a/llvm/test/CodeGen/PowerPC/builtins-ppc-p10permute.ll +++ b/llvm/test/CodeGen/PowerPC/builtins-ppc-p10permute.ll @@ -170,67 +170,67 @@ entry: } declare <2 x i64> @llvm.ppc.altivec.vinsdrx(<2 x i64>, i64, i64) -define <16 x i8> @testVINSBVLX(<16 x i8> %a, i64 %b, <16 x i8> %c) { +define <16 x i8> @testVINSBVLX(<16 x i8> %a, i32 %b, <16 x i8> %c) { ; CHECK-LABEL: testVINSBVLX: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vinsbvlx v2, r5, v3 ; CHECK-NEXT: blr entry: - %0 = tail call <16 x i8> @llvm.ppc.altivec.vinsbvlx(<16 x i8> %a, i64 %b, <16 x i8> %c) + %0 = tail call <16 x i8> @llvm.ppc.altivec.vinsbvlx(<16 x i8> %a, i32 %b, <16 x i8> %c) ret <16 x i8> %0 } -declare <16 x i8> @llvm.ppc.altivec.vinsbvlx(<16 x i8>, i64, <16 x i8>) +declare <16 x i8> @llvm.ppc.altivec.vinsbvlx(<16 x i8>, i32, <16 x i8>) -define <16 x i8> @testVINSBVRX(<16 x i8> %a, i64 %b, <16 x i8> %c) { +define <16 x i8> @testVINSBVRX(<16 x i8> %a, i32 %b, <16 x i8> %c) { ; CHECK-LABEL: testVINSBVRX: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vinsbvrx v2, r5, v3 ; CHECK-NEXT: blr entry: - %0 = tail call <16 x i8> @llvm.ppc.altivec.vinsbvrx(<16 x i8> %a, i64 %b, <16 x i8> %c) + %0 = tail call <16 x i8> @llvm.ppc.altivec.vinsbvrx(<16 x i8> %a, i32 %b, <16 x i8> %c) ret <16 x i8> %0 } -declare <16 x i8> @llvm.ppc.altivec.vinsbvrx(<16 x i8>, i64, <16 x i8>) +declare <16 x i8> @llvm.ppc.altivec.vinsbvrx(<16 x i8>, i32, <16 x i8>) -define <8 x i16> @testVINSHVLX(<8 x i16> %a, i64 %b, <8 x i16> %c) { +define <8 x i16> @testVINSHVLX(<8 x i16> %a, i32 %b, <8 x i16> %c) { ; CHECK-LABEL: testVINSHVLX: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vinshvlx v2, r5, v3 ; CHECK-NEXT: blr entry: - %0 = tail call <8 x i16> @llvm.ppc.altivec.vinshvlx(<8 x i16> %a, i64 %b, <8 x i16> %c) + %0 = tail call <8 x i16> @llvm.ppc.altivec.vinshvlx(<8 x i16> %a, i32 %b, <8 x i16> %c) ret <8 x i16> %0 } -declare <8 x i16> @llvm.ppc.altivec.vinshvlx(<8 x i16>, i64, <8 x i16>) +declare <8 x i16> @llvm.ppc.altivec.vinshvlx(<8 x i16>, i32, <8 x i16>) -define <8 x i16> @testVINSHVRX(<8 x i16> %a, i64 %b, <8 x i16> %c) { +define <8 x i16> @testVINSHVRX(<8 x i16> %a, i32 %b, <8 x i16> %c) { entry: - %0 = tail call <8 x i16> @llvm.ppc.altivec.vinshvrx(<8 x i16> %a, i64 %b, <8 x i16> %c) + %0 = tail call <8 x i16> @llvm.ppc.altivec.vinshvrx(<8 x i16> %a, i32 %b, <8 x i16> %c) ret <8 x i16> %0 } -declare <8 x i16> @llvm.ppc.altivec.vinshvrx(<8 x i16>, i64, <8 x i16>) +declare <8 x i16> @llvm.ppc.altivec.vinshvrx(<8 x i16>, i32, <8 x i16>) -define <4 x i32> @testVINSWVLX(<4 x i32> %a, i64 %b, <4 x i32> %c) { +define <4 x i32> @testVINSWVLX(<4 x i32> %a, i32 %b, <4 x i32> %c) { ; CHECK-LABEL: testVINSWVLX: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vinswvlx v2, r5, v3 ; CHECK-NEXT: blr entry: - %0 = tail call <4 x i32> @llvm.ppc.altivec.vinswvlx(<4 x i32> %a, i64 %b, <4 x i32> %c) + %0 = tail call <4 x i32> @llvm.ppc.altivec.vinswvlx(<4 x i32> %a, i32 %b, <4 x i32> %c) ret <4 x i32> %0 } -declare <4 x i32> @llvm.ppc.altivec.vinswvlx(<4 x i32>, i64, <4 x i32>) +declare <4 x i32> @llvm.ppc.altivec.vinswvlx(<4 x i32>, i32, <4 x i32>) -define <4 x i32> @testVINSWVRX(<4 x i32> %a, i64 %b, <4 x i32> %c) { +define <4 x i32> @testVINSWVRX(<4 x i32> %a, i32 %b, <4 x i32> %c) { ; CHECK-LABEL: testVINSWVRX: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vinswvrx v2, r5, v3 ; CHECK-NEXT: blr entry: - %0 = tail call <4 x i32> @llvm.ppc.altivec.vinswvrx(<4 x i32> %a, i64 %b, <4 x i32> %c) + %0 = tail call <4 x i32> @llvm.ppc.altivec.vinswvrx(<4 x i32> %a, i32 %b, <4 x i32> %c) ret <4 x i32> %0 } -declare <4 x i32> @llvm.ppc.altivec.vinswvrx(<4 x i32>, i64, <4 x i32>) +declare <4 x i32> @llvm.ppc.altivec.vinswvrx(<4 x i32>, i32, <4 x i32>) define <4 x i32> @testVINSW(<4 x i32> %a, i32 %b) { ; CHECK-LABEL: testVINSW: _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
