apazos added inline comments.
================ Comment at: llvm/lib/Target/RISCV/RISCVFrameLowering.cpp:95 + .addReg(RISCV::X18) + .addImm(0); +} ---------------- There are thee things to observe here and other reviewers might have some additional comments: - RISC-V does not have a reserved platform register like AAch64. The patch uses one of the RISC-V callee saved registers, x18, which happens to coincide with AArch64's register. It is possible to select another register, and additional checks for the flag combo "-fsanitize=shadow-call-stack -ffixed-xxxx" will have to be added. - The return address is saved on both the SCS (whose location is protected/hidden) and also in the regular stack. But the return from a function uses the value saved on SCS. The understanding is that not saving it in the regular stack can impact debugging. - The SCS is ascending, while the regular stack, by RISC-V convention, is descending. The SCS is not used for passing parameters between calls like the regular stack, so it seems to be ok. But this can be changed too. AArch64 's SCS is also ascending. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D84414/new/ https://reviews.llvm.org/D84414 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
