Author: Amy Kwan Date: 2020-09-23T16:49:40-04:00 New Revision: 2e7117f847708d2fd1ff2d2961c3439470532b80
URL: https://github.com/llvm/llvm-project/commit/2e7117f847708d2fd1ff2d2961c3439470532b80 DIFF: https://github.com/llvm/llvm-project/commit/2e7117f847708d2fd1ff2d2961c3439470532b80.diff LOG: [PowerPC] Implement the 128-bit vec_[all|any]_[eq | ne | lt | gt | le | ge] builtins in Clang/LLVM This patch implements the vec_[all|any]_[eq | ne | lt | gt | le | ge] builtins for vector signed/unsigned __int128. Differential Revision: https://reviews.llvm.org/D87910 Added: Modified: clang/include/clang/Basic/BuiltinsPPC.def clang/lib/CodeGen/CGExprScalar.cpp clang/lib/Headers/altivec.h clang/test/CodeGen/builtins-ppc-p10vector.c llvm/include/llvm/IR/IntrinsicsPowerPC.td llvm/lib/Target/PowerPC/PPCISelLowering.cpp llvm/test/CodeGen/PowerPC/vec_cmpq.ll Removed: ################################################################################ diff --git a/clang/include/clang/Basic/BuiltinsPPC.def b/clang/include/clang/Basic/BuiltinsPPC.def index e236ebdd7082..91c3f040cb48 100644 --- a/clang/include/clang/Basic/BuiltinsPPC.def +++ b/clang/include/clang/Basic/BuiltinsPPC.def @@ -160,6 +160,9 @@ BUILTIN(__builtin_altivec_vcmpgtfp, "V4iV4fV4f", "") BUILTIN(__builtin_altivec_vcmpequq, "V1LLLiV1ULLLiV1ULLLi", "") BUILTIN(__builtin_altivec_vcmpgtsq, "V1LLLiV1SLLLiV1SLLLi", "") BUILTIN(__builtin_altivec_vcmpgtuq, "V1LLLiV1ULLLiV1ULLLi", "") +BUILTIN(__builtin_altivec_vcmpequq_p, "iiV1ULLLiV1LLLi", "") +BUILTIN(__builtin_altivec_vcmpgtsq_p, "iiV1SLLLiV1SLLLi", "") +BUILTIN(__builtin_altivec_vcmpgtuq_p, "iiV1ULLLiV1ULLLi", "") BUILTIN(__builtin_altivec_vmaxsb, "V16ScV16ScV16Sc", "") BUILTIN(__builtin_altivec_vmaxub, "V16UcV16UcV16Uc", "") diff --git a/clang/lib/CodeGen/CGExprScalar.cpp b/clang/lib/CodeGen/CGExprScalar.cpp index da24ff273602..cee2210e74c1 100644 --- a/clang/lib/CodeGen/CGExprScalar.cpp +++ b/clang/lib/CodeGen/CGExprScalar.cpp @@ -3882,6 +3882,12 @@ static llvm::Intrinsic::ID GetIntrinsic(IntrinsicType IT, case BuiltinType::Double: return (IT == VCMPEQ) ? llvm::Intrinsic::ppc_vsx_xvcmpeqdp_p : llvm::Intrinsic::ppc_vsx_xvcmpgtdp_p; + case BuiltinType::UInt128: + return (IT == VCMPEQ) ? llvm::Intrinsic::ppc_altivec_vcmpequq_p + : llvm::Intrinsic::ppc_altivec_vcmpgtuq_p; + case BuiltinType::Int128: + return (IT == VCMPEQ) ? llvm::Intrinsic::ppc_altivec_vcmpequq_p + : llvm::Intrinsic::ppc_altivec_vcmpgtsq_p; } } diff --git a/clang/lib/Headers/altivec.h b/clang/lib/Headers/altivec.h index d1fcde741a37..03e82c8ae7e0 100644 --- a/clang/lib/Headers/altivec.h +++ b/clang/lib/Headers/altivec.h @@ -14186,6 +14186,18 @@ static __inline__ int __ATTRS_o_ai vec_all_eq(vector double __a, } #endif +#ifdef __POWER10_VECTOR__ +static __inline__ int __ATTRS_o_ai vec_all_eq(vector signed __int128 __a, + vector signed __int128 __b) { + return __builtin_altivec_vcmpequq_p(__CR6_LT, __a, __b); +} + +static __inline__ int __ATTRS_o_ai vec_all_eq(vector unsigned __int128 __a, + vector unsigned __int128 __b) { + return __builtin_altivec_vcmpequq_p(__CR6_LT, __a, __b); +} +#endif + /* vec_all_ge */ static __inline__ int __ATTRS_o_ai vec_all_ge(vector signed char __a, @@ -14357,6 +14369,18 @@ static __inline__ int __ATTRS_o_ai vec_all_ge(vector double __a, } #endif +#ifdef __POWER10_VECTOR__ +static __inline__ int __ATTRS_o_ai vec_all_ge(vector signed __int128 __a, + vector signed __int128 __b) { + return __builtin_altivec_vcmpgtsq_p(__CR6_EQ, __b, __a); +} + +static __inline__ int __ATTRS_o_ai vec_all_ge(vector unsigned __int128 __a, + vector unsigned __int128 __b) { + return __builtin_altivec_vcmpgtuq_p(__CR6_EQ, __b, __a); +} +#endif + /* vec_all_gt */ static __inline__ int __ATTRS_o_ai vec_all_gt(vector signed char __a, @@ -14528,6 +14552,18 @@ static __inline__ int __ATTRS_o_ai vec_all_gt(vector double __a, } #endif +#ifdef __POWER10_VECTOR__ +static __inline__ int __ATTRS_o_ai vec_all_gt(vector signed __int128 __a, + vector signed __int128 __b) { + return __builtin_altivec_vcmpgtsq_p(__CR6_LT, __a, __b); +} + +static __inline__ int __ATTRS_o_ai vec_all_gt(vector unsigned __int128 __a, + vector unsigned __int128 __b) { + return __builtin_altivec_vcmpgtuq_p(__CR6_LT, __a, __b); +} +#endif + /* vec_all_in */ static __inline__ int __attribute__((__always_inline__)) @@ -14707,6 +14743,18 @@ static __inline__ int __ATTRS_o_ai vec_all_le(vector double __a, } #endif +#ifdef __POWER10_VECTOR__ +static __inline__ int __ATTRS_o_ai vec_all_le(vector signed __int128 __a, + vector signed __int128 __b) { + return __builtin_altivec_vcmpgtsq_p(__CR6_EQ, __a, __b); +} + +static __inline__ int __ATTRS_o_ai vec_all_le(vector unsigned __int128 __a, + vector unsigned __int128 __b) { + return __builtin_altivec_vcmpgtuq_p(__CR6_EQ, __a, __b); +} +#endif + /* vec_all_lt */ static __inline__ int __ATTRS_o_ai vec_all_lt(vector signed char __a, @@ -14879,6 +14927,18 @@ static __inline__ int __ATTRS_o_ai vec_all_lt(vector double __a, } #endif +#ifdef __POWER10_VECTOR__ +static __inline__ int __ATTRS_o_ai vec_all_lt(vector signed __int128 __a, + vector signed __int128 __b) { + return __builtin_altivec_vcmpgtsq_p(__CR6_LT, __b, __a); +} + +static __inline__ int __ATTRS_o_ai vec_all_lt(vector unsigned __int128 __a, + vector unsigned __int128 __b) { + return __builtin_altivec_vcmpgtuq_p(__CR6_LT, __b, __a); +} +#endif + /* vec_all_nan */ static __inline__ int __ATTRS_o_ai vec_all_nan(vector float __a) { @@ -15083,6 +15143,18 @@ static __inline__ int __ATTRS_o_ai vec_all_ne(vector double __a, } #endif +#ifdef __POWER10_VECTOR__ +static __inline__ int __ATTRS_o_ai vec_all_ne(vector signed __int128 __a, + vector signed __int128 __b) { + return __builtin_altivec_vcmpequq_p(__CR6_EQ, __a, __b); +} + +static __inline__ int __ATTRS_o_ai vec_all_ne(vector unsigned __int128 __a, + vector unsigned __int128 __b) { + return __builtin_altivec_vcmpequq_p(__CR6_EQ, __a, __b); +} +#endif + /* vec_all_nge */ static __inline__ int __ATTRS_o_ai vec_all_nge(vector float __a, @@ -15328,6 +15400,18 @@ static __inline__ int __ATTRS_o_ai vec_any_eq(vector double __a, } #endif +#ifdef __POWER10_VECTOR__ +static __inline__ int __ATTRS_o_ai vec_any_eq(vector signed __int128 __a, + vector signed __int128 __b) { + return __builtin_altivec_vcmpequq_p(__CR6_EQ_REV, __a, __b); +} + +static __inline__ int __ATTRS_o_ai vec_any_eq(vector unsigned __int128 __a, + vector unsigned __int128 __b) { + return __builtin_altivec_vcmpequq_p(__CR6_EQ_REV, __a, __b); +} +#endif + /* vec_any_ge */ static __inline__ int __ATTRS_o_ai vec_any_ge(vector signed char __a, @@ -15507,6 +15591,18 @@ static __inline__ int __ATTRS_o_ai vec_any_ge(vector double __a, } #endif +#ifdef __POWER10_VECTOR__ +static __inline__ int __ATTRS_o_ai vec_any_ge(vector signed __int128 __a, + vector signed __int128 __b) { + return __builtin_altivec_vcmpgtsq_p(__CR6_LT_REV, __b, __a); +} + +static __inline__ int __ATTRS_o_ai vec_any_ge(vector unsigned __int128 __a, + vector unsigned __int128 __b) { + return __builtin_altivec_vcmpgtuq_p(__CR6_LT_REV, __b, __a); +} +#endif + /* vec_any_gt */ static __inline__ int __ATTRS_o_ai vec_any_gt(vector signed char __a, @@ -15686,6 +15782,18 @@ static __inline__ int __ATTRS_o_ai vec_any_gt(vector double __a, } #endif +#ifdef __POWER10_VECTOR__ +static __inline__ int __ATTRS_o_ai vec_any_gt(vector signed __int128 __a, + vector signed __int128 __b) { + return __builtin_altivec_vcmpgtsq_p(__CR6_EQ_REV, __a, __b); +} + +static __inline__ int __ATTRS_o_ai vec_any_gt(vector unsigned __int128 __a, + vector unsigned __int128 __b) { + return __builtin_altivec_vcmpgtuq_p(__CR6_EQ_REV, __a, __b); +} +#endif + /* vec_any_le */ static __inline__ int __ATTRS_o_ai vec_any_le(vector signed char __a, @@ -15865,6 +15973,18 @@ static __inline__ int __ATTRS_o_ai vec_any_le(vector double __a, } #endif +#ifdef __POWER10_VECTOR__ +static __inline__ int __ATTRS_o_ai vec_any_le(vector signed __int128 __a, + vector signed __int128 __b) { + return __builtin_altivec_vcmpgtsq_p(__CR6_LT_REV, __a, __b); +} + +static __inline__ int __ATTRS_o_ai vec_any_le(vector unsigned __int128 __a, + vector unsigned __int128 __b) { + return __builtin_altivec_vcmpgtuq_p(__CR6_LT_REV, __a, __b); +} +#endif + /* vec_any_lt */ static __inline__ int __ATTRS_o_ai vec_any_lt(vector signed char __a, @@ -16044,6 +16164,18 @@ static __inline__ int __ATTRS_o_ai vec_any_lt(vector double __a, } #endif +#ifdef __POWER10_VECTOR__ +static __inline__ int __ATTRS_o_ai vec_any_lt(vector signed __int128 __a, + vector signed __int128 __b) { + return __builtin_altivec_vcmpgtsq_p(__CR6_EQ_REV, __b, __a); +} + +static __inline__ int __ATTRS_o_ai vec_any_lt(vector unsigned __int128 __a, + vector unsigned __int128 __b) { + return __builtin_altivec_vcmpgtuq_p(__CR6_EQ_REV, __b, __a); +} +#endif + /* vec_any_nan */ static __inline__ int __attribute__((__always_inline__)) @@ -16239,6 +16371,18 @@ static __inline__ int __ATTRS_o_ai vec_any_ne(vector double __a, } #endif +#ifdef __POWER10_VECTOR__ +static __inline__ int __ATTRS_o_ai vec_any_ne(vector signed __int128 __a, + vector signed __int128 __b) { + return __builtin_altivec_vcmpequq_p(__CR6_LT_REV, __a, __b); +} + +static __inline__ int __ATTRS_o_ai vec_any_ne(vector unsigned __int128 __a, + vector unsigned __int128 __b) { + return __builtin_altivec_vcmpequq_p(__CR6_LT_REV, __a, __b); +} +#endif + /* vec_any_nge */ static __inline__ int __attribute__((__always_inline__)) diff --git a/clang/test/CodeGen/builtins-ppc-p10vector.c b/clang/test/CodeGen/builtins-ppc-p10vector.c index 084b57957464..3fc931357298 100644 --- a/clang/test/CodeGen/builtins-ppc-p10vector.c +++ b/clang/test/CodeGen/builtins-ppc-p10vector.c @@ -1589,3 +1589,171 @@ vector bool __int128 test_vec_cmple_u128(void) { // CHECK-NEXT: ret <1 x i128> return vec_cmple(vui128a, vui128b); } + +int test_vec_any_eq_u128(void) { + // CHECK-LABEL: @test_vec_any_eq_u128( + // CHECK: call i32 @llvm.ppc.altivec.vcmpequq.p(i32 1, <1 x i128> %2, <1 x i128> %3) + // CHECK-NEXT: ret i32 + return vec_any_eq(vui128a, vui128b); +} + +int test_vec_any_eq_s128(void) { + // CHECK-LABEL: @test_vec_any_eq_s128( + // CHECK: call i32 @llvm.ppc.altivec.vcmpequq.p(i32 1, <1 x i128> %2, <1 x i128> %3) + // CHECK-NEXT: ret i32 + return vec_any_eq(vsi128a, vsi128b); +} + +int test_vec_any_ne_s128(void) { + // CHECK-LABEL: @test_vec_any_ne_s128( + // CHECK: call i32 @llvm.ppc.altivec.vcmpequq.p(i32 3, <1 x i128> %2, <1 x i128> %3) + // CHECK-NEXT: ret i32 + return vec_any_ne(vsi128a, vsi128b); +} + +int test_vec_any_ne_u128(void) { + // CHECK-LABEL: @test_vec_any_ne_u128( + // CHECK: call i32 @llvm.ppc.altivec.vcmpequq.p(i32 3, <1 x i128> %2, <1 x i128> %3) + // CHECK-NEXT: ret i32 + return vec_any_ne(vui128a, vui128b); +} + +int test_vec_any_lt_s128(void) { + // CHECK-LABEL: @test_vec_any_lt_s128( + // CHECK: call i32 @llvm.ppc.altivec.vcmpgtsq.p(i32 1, <1 x i128> %2, <1 x i128> %3) + // CHECK-NEXT: ret i32 + return vec_any_lt(vsi128a, vsi128b); +} + +int test_vec_any_lt_u128(void) { + // CHECK-LABEL: @test_vec_any_lt_u128( + // CHECK: call i32 @llvm.ppc.altivec.vcmpgtuq.p(i32 1, <1 x i128> %2, <1 x i128> %3) + // CHECK-NEXT: ret i32 + return vec_any_lt(vui128a, vui128b); +} + +int test_vec_any_gt_s128(void) { + // CHECK-LABEL: @test_vec_any_gt_s128( + // CHECK: call i32 @llvm.ppc.altivec.vcmpgtsq.p(i32 1, <1 x i128> %2, <1 x i128> %3) + // CHECK-NEXT: ret i32 + return vec_any_gt(vsi128a, vsi128b); +} + +int test_vec_any_gt_u128(void) { + // CHECK-LABEL: @test_vec_any_gt_u128( + // CHECK: call i32 @llvm.ppc.altivec.vcmpgtuq.p(i32 1, <1 x i128> %2, <1 x i128> %3) + // CHECK-NEXT: ret i32 + return vec_any_gt(vui128a, vui128b); +} + +int test_vec_any_le_s128(void) { + // CHECK-LABEL: @test_vec_any_le_s128( + // CHECK: call i32 @llvm.ppc.altivec.vcmpgtsq.p(i32 3, <1 x i128> %2, <1 x i128> %3) + // CHECK-NEXT: ret i32 + return vec_any_le(vsi128a, vsi128b); +} + +int test_vec_any_le_u128(void) { + // CHECK-LABEL: @test_vec_any_le_u128( + // CHECK: call i32 @llvm.ppc.altivec.vcmpgtuq.p(i32 3, <1 x i128> %2, <1 x i128> %3) + // CHECK-NEXT: ret i32 + return vec_any_le(vui128a, vui128b); +} + +int test_vec_any_ge_s128(void) { + // CHECK-LABEL: @test_vec_any_ge_s128( + // CHECK: call i32 @llvm.ppc.altivec.vcmpgtsq.p(i32 3, <1 x i128> %2, <1 x i128> %3) + // CHECK-NEXT: ret i32 + return vec_any_ge(vsi128a, vsi128b); +} + +int test_vec_any_ge_u128(void) { + // CHECK-LABEL: @test_vec_any_ge_u128( + // CHECK: call i32 @llvm.ppc.altivec.vcmpgtuq.p(i32 3, <1 x i128> %2, <1 x i128> %3) + // CHECK-NEXT: ret i32 + return vec_any_ge(vui128a, vui128b); +} + +int test_vec_all_eq_s128(void) { + // CHECK-LABEL: @test_vec_all_eq_s128( + // CHECK: call i32 @llvm.ppc.altivec.vcmpequq.p(i32 2, <1 x i128> %2, <1 x i128> %3) + // CHECK-NEXT: ret i32 + return vec_all_eq(vsi128a, vsi128b); +} + +int test_vec_all_eq_u128(void) { + // CHECK-LABEL: @test_vec_all_eq_u128( + // CHECK: call i32 @llvm.ppc.altivec.vcmpequq.p(i32 2, <1 x i128> %2, <1 x i128> %3) + // CHECK-NEXT: ret i32 + return vec_all_eq(vui128a, vui128b); +} + +int test_vec_all_ne_s128(void) { + // CHECK-LABEL: @test_vec_all_ne_s128( + // CHECK: call i32 @llvm.ppc.altivec.vcmpequq.p(i32 0, <1 x i128> %2, <1 x i128> %3) + // CHECK-NEXT: ret i32 + return vec_all_ne(vsi128a, vsi128b); +} + +int test_vec_all_ne_u128(void) { + // CHECK-LABEL: @test_vec_all_ne_u128( + // CHECK: call i32 @llvm.ppc.altivec.vcmpequq.p(i32 0, <1 x i128> %2, <1 x i128> %3) + // CHECK-NEXT: ret i32 + return vec_all_ne(vui128a, vui128b); +} + +int test_vec_all_lt_s128(void) { + // CHECK-LABEL: @test_vec_all_lt_s128( + // CHECK: call i32 @llvm.ppc.altivec.vcmpgtsq.p(i32 2, <1 x i128> %2, <1 x i128> %3) + // CHECK-NEXT: ret i32 + return vec_all_lt(vsi128a, vsi128b); +} + +int test_vec_all_lt_u128(void) { + // CHECK-LABEL: @test_vec_all_lt_u128( + // CHECK: call i32 @llvm.ppc.altivec.vcmpgtuq.p(i32 2, <1 x i128> %2, <1 x i128> %3) + // CHECK: ret i32 + return vec_all_lt(vui128a, vui128b); +} + +int test_vec_all_gt_s128(void) { + // CHECK-LABEL: @test_vec_all_gt_s128( + // CHECK: call i32 @llvm.ppc.altivec.vcmpgtsq.p(i32 2, <1 x i128> %2, <1 x i128> %3) + // CHECK-NEXT: ret i32 + return vec_all_gt(vsi128a, vsi128b); +} + +int test_vec_all_gt_u128(void) { + // CHECK-LABEL: @test_vec_all_gt_u128( + // CHECK: call i32 @llvm.ppc.altivec.vcmpgtuq.p(i32 2, <1 x i128> %2, <1 x i128> %3) + // CHECK-NEXT: ret i32 + return vec_all_gt(vui128a, vui128b); +} + +int test_vec_all_le_s128(void) { + // CHECK-LABEL: @test_vec_all_le_s128( + // CHECK: call i32 @llvm.ppc.altivec.vcmpgtsq.p(i32 0, <1 x i128> %2, <1 x i128> %3) + // CHECK-NEXT: ret i32 + return vec_all_le(vsi128a, vsi128b); +} + +int test_vec_all_le_u128(void) { + // CHECK-LABEL: @test_vec_all_le_u128( + // CHECK: call i32 @llvm.ppc.altivec.vcmpgtuq.p(i32 0, <1 x i128> %2, <1 x i128> %3) + // CHECK-NEXT: ret i32 + return vec_all_le(vui128a, vui128b); +} + +int test_vec_all_ge_s128(void) { + // CHECK-LABEL: @test_vec_all_ge_s128( + // CHECK: call i32 @llvm.ppc.altivec.vcmpgtsq.p(i32 0, <1 x i128> %2, <1 x i128> %3) + // CHECK-NEXT: ret i32 + return vec_all_ge(vsi128a, vsi128b); +} + +int test_vec_all_ge_u128(void) { + // CHECK-LABEL: @test_vec_all_ge_u128( + // CHECK: call i32 @llvm.ppc.altivec.vcmpgtuq.p(i32 0, <1 x i128> %2, <1 x i128> %3) + // CHECK-NEXT: ret i32 + return vec_all_ge(vui128a, vui128b); +} diff --git a/llvm/include/llvm/IR/IntrinsicsPowerPC.td b/llvm/include/llvm/IR/IntrinsicsPowerPC.td index 99fd1973b82d..7b11555296a4 100644 --- a/llvm/include/llvm/IR/IntrinsicsPowerPC.td +++ b/llvm/include/llvm/IR/IntrinsicsPowerPC.td @@ -370,6 +370,18 @@ let TargetPrefix = "ppc" in { // All intrinsics start with "llvm.ppc.". def int_ppc_altivec_vcmpgtuq : GCCBuiltin<"__builtin_altivec_vcmpgtuq">, Intrinsic<[llvm_v1i128_ty], [llvm_v1i128_ty, llvm_v1i128_ty], [IntrNoMem]>; + def int_ppc_altivec_vcmpequq_p : GCCBuiltin<"__builtin_altivec_vcmpequq_p">, + Intrinsic<[llvm_i32_ty], + [llvm_i32_ty,llvm_v1i128_ty,llvm_v1i128_ty], + [IntrNoMem]>; + def int_ppc_altivec_vcmpgtsq_p : GCCBuiltin<"__builtin_altivec_vcmpgtsq_p">, + Intrinsic<[llvm_i32_ty], + [llvm_i32_ty,llvm_v1i128_ty,llvm_v1i128_ty], + [IntrNoMem]>; + def int_ppc_altivec_vcmpgtuq_p : GCCBuiltin<"__builtin_altivec_vcmpgtuq_p">, + Intrinsic<[llvm_i32_ty], + [llvm_i32_ty,llvm_v1i128_ty,llvm_v1i128_ty], + [IntrNoMem]>; // Predicate Comparisons. The first operand specifies interpretation of CR6. def int_ppc_altivec_vcmpbfp_p : GCCBuiltin<"__builtin_altivec_vcmpbfp_p">, diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index 5a75d229e0dd..bf0bea5f1233 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -10358,6 +10358,26 @@ static bool getVectorCompareInfo(SDValue Intrin, int &CompareOpc, else return false; break; + case Intrinsic::ppc_altivec_vcmpequq_p: + case Intrinsic::ppc_altivec_vcmpgtsq_p: + case Intrinsic::ppc_altivec_vcmpgtuq_p: + if (!Subtarget.isISA3_1()) + return false; + switch (IntrinsicID) { + default: + llvm_unreachable("Unknown comparison intrinsic."); + case Intrinsic::ppc_altivec_vcmpequq_p: + CompareOpc = 455; + break; + case Intrinsic::ppc_altivec_vcmpgtsq_p: + CompareOpc = 903; + break; + case Intrinsic::ppc_altivec_vcmpgtuq_p: + CompareOpc = 647; + break; + } + isDot = true; + break; } return true; } @@ -15224,16 +15244,19 @@ void PPCTargetLowering::computeKnownBitsForTargetNode(const SDValue Op, case Intrinsic::ppc_altivec_vcmpequh_p: case Intrinsic::ppc_altivec_vcmpequw_p: case Intrinsic::ppc_altivec_vcmpequd_p: + case Intrinsic::ppc_altivec_vcmpequq_p: case Intrinsic::ppc_altivec_vcmpgefp_p: case Intrinsic::ppc_altivec_vcmpgtfp_p: case Intrinsic::ppc_altivec_vcmpgtsb_p: case Intrinsic::ppc_altivec_vcmpgtsh_p: case Intrinsic::ppc_altivec_vcmpgtsw_p: case Intrinsic::ppc_altivec_vcmpgtsd_p: + case Intrinsic::ppc_altivec_vcmpgtsq_p: case Intrinsic::ppc_altivec_vcmpgtub_p: case Intrinsic::ppc_altivec_vcmpgtuh_p: case Intrinsic::ppc_altivec_vcmpgtuw_p: case Intrinsic::ppc_altivec_vcmpgtud_p: + case Intrinsic::ppc_altivec_vcmpgtuq_p: Known.Zero = ~1U; // All bits but the low one are known to be zero. break; } diff --git a/llvm/test/CodeGen/PowerPC/vec_cmpq.ll b/llvm/test/CodeGen/PowerPC/vec_cmpq.ll index 6cddf7cee794..c110b8cedaeb 100644 --- a/llvm/test/CodeGen/PowerPC/vec_cmpq.ll +++ b/llvm/test/CodeGen/PowerPC/vec_cmpq.ll @@ -248,3 +248,31 @@ define <1 x i128> @test_vcmpgtuq(<1 x i128> %x, <1 x i128> %y) { ; CHECK: vcmpgtuq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} ; CHECK: blr } + +declare i32 @llvm.ppc.altivec.vcmpequq.p(i32, <1 x i128>, <1 x i128>) nounwind readnone +declare i32 @llvm.ppc.altivec.vcmpgtsq.p(i32, <1 x i128>, <1 x i128>) nounwind readnone +declare i32 @llvm.ppc.altivec.vcmpgtuq.p(i32, <1 x i128>, <1 x i128>) nounwind readnone + +define i32 @test_vcmpequq_p(<1 x i128> %x, <1 x i128> %y) { + %tmp = tail call i32 @llvm.ppc.altivec.vcmpequq.p(i32 2, <1 x i128> %x, <1 x i128> %y) + ret i32 %tmp +; CHECK-LABEL: test_vcmpequq_p: +; CHECK: vcmpequq. {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} +; CHECK: blr +} + +define i32 @test_vcmpgtsq_p(<1 x i128> %x, <1 x i128> %y) { + %tmp = tail call i32 @llvm.ppc.altivec.vcmpgtsq.p(i32 2, <1 x i128> %x, <1 x i128> %y) + ret i32 %tmp +; CHECK-LABEL: test_vcmpgtsq_p +; CHECK: vcmpgtsq. {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} +; CHECK: blr +} + +define i32 @test_vcmpgtuq_p(<1 x i128> %x, <1 x i128> %y) { + %tmp = tail call i32 @llvm.ppc.altivec.vcmpgtuq.p(i32 2, <1 x i128> %x, <1 x i128> %y) + ret i32 %tmp +; CHECK-LABEL: test_vcmpgtuq_p +; CHECK: vcmpgtuq. {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} +; CHECK: blr +} _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
