keryell added a comment.
Herald added a subscriber: dexonsmith.
An FPGA programmer is hitting this issue from your unit test:
c++
signed _ExtInt(1) m; // expected-error{{signed _ExtInt must have a bit size
of at least 2}}
Why do you not allow a type able to represent `{-1, 0}`?
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D73967/new/
https://reviews.llvm.org/D73967
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