Author: Levy Hsu Date: 2021-04-02T10:58:45-07:00 New Revision: b001d574d7d94bcf1508fa4cdc22e02a0bf4adea
URL: https://github.com/llvm/llvm-project/commit/b001d574d7d94bcf1508fa4cdc22e02a0bf4adea DIFF: https://github.com/llvm/llvm-project/commit/b001d574d7d94bcf1508fa4cdc22e02a0bf4adea.diff LOG: [RISCV] Add IR intrinsic for Zbr extension Implementation for RISC-V Zbr extension intrinsic. Header files are included in separate patch in case the name needs to be changed RV32 / 64: crc32b crc32h crc32w crc32cb crc32ch crc32cw RV64 Only: crc32d crc32cd Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D99009 Added: clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbr.c clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbr.c llvm/test/CodeGen/RISCV/rv32zbr.ll llvm/test/CodeGen/RISCV/rv64zbr.ll Modified: clang/include/clang/Basic/BuiltinsRISCV.def clang/include/clang/Basic/DiagnosticSemaKinds.td clang/lib/CodeGen/CGBuiltin.cpp clang/lib/Sema/SemaChecking.cpp llvm/include/llvm/IR/IntrinsicsRISCV.td llvm/lib/Target/RISCV/RISCVInstrInfo.td llvm/lib/Target/RISCV/RISCVInstrInfoB.td Removed: ################################################################################ diff --git a/clang/include/clang/Basic/BuiltinsRISCV.def b/clang/include/clang/Basic/BuiltinsRISCV.def index c91b3d1b1f5c1..7197b3df26212 100644 --- a/clang/include/clang/Basic/BuiltinsRISCV.def +++ b/clang/include/clang/Basic/BuiltinsRISCV.def @@ -17,5 +17,15 @@ #include "clang/Basic/riscv_vector_builtins.inc" +// Zbr extension +TARGET_BUILTIN(__builtin_riscv_crc32_b, "LiLi", "nc", "experimental-zbr") +TARGET_BUILTIN(__builtin_riscv_crc32_h, "LiLi", "nc", "experimental-zbr") +TARGET_BUILTIN(__builtin_riscv_crc32_w, "LiLi", "nc", "experimental-zbr") +TARGET_BUILTIN(__builtin_riscv_crc32c_b, "LiLi", "nc", "experimental-zbr") +TARGET_BUILTIN(__builtin_riscv_crc32c_h, "LiLi", "nc", "experimental-zbr") +TARGET_BUILTIN(__builtin_riscv_crc32c_w, "LiLi", "nc", "experimental-zbr") +TARGET_BUILTIN(__builtin_riscv_crc32_d, "LiLi", "nc", "experimental-zbr") +TARGET_BUILTIN(__builtin_riscv_crc32c_d, "LiLi", "nc", "experimental-zbr") + #undef BUILTIN #undef TARGET_BUILTIN diff --git a/clang/include/clang/Basic/DiagnosticSemaKinds.td b/clang/include/clang/Basic/DiagnosticSemaKinds.td index d51a01837fc93..91246ccba6fa0 100644 --- a/clang/include/clang/Basic/DiagnosticSemaKinds.td +++ b/clang/include/clang/Basic/DiagnosticSemaKinds.td @@ -11185,7 +11185,7 @@ def warn_tcb_enforcement_violation : Warning< "calling %0 is a violation of trusted computing base '%1'">, InGroup<DiagGroup<"tcb-enforcement">>; -// RISC-V V-extension -def err_riscvv_builtin_requires_v : Error< - "builtin requires 'V' extension support to be enabled">; +// RISC-V builtin required extension warning +def err_riscv_builtin_requires_extension : Error< + "builtin requires %0 extension support to be enabled">; } // end of sema component. diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp index 86ea4ac28ae86..fc5b7ce6bcca2 100644 --- a/clang/lib/CodeGen/CGBuiltin.cpp +++ b/clang/lib/CodeGen/CGBuiltin.cpp @@ -17876,6 +17876,44 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned BuiltinID, llvm::SmallVector<llvm::Type *, 2> IntrinsicTypes; switch (BuiltinID) { #include "clang/Basic/riscv_vector_builtin_cg.inc" + + // Zbr + case RISCV::BI__builtin_riscv_crc32_b: + ID = Intrinsic::riscv_crc32_b; + IntrinsicTypes = {ResultType}; + break; + case RISCV::BI__builtin_riscv_crc32_h: + ID = Intrinsic::riscv_crc32_h; + IntrinsicTypes = {ResultType}; + break; + case RISCV::BI__builtin_riscv_crc32_w: + ID = Intrinsic::riscv_crc32_w; + IntrinsicTypes = {ResultType}; + break; + case RISCV::BI__builtin_riscv_crc32_d: + ID = Intrinsic::riscv_crc32_d; + IntrinsicTypes = {ResultType}; + break; + case RISCV::BI__builtin_riscv_crc32c_b: + ID = Intrinsic::riscv_crc32c_b; + IntrinsicTypes = {ResultType}; + break; + case RISCV::BI__builtin_riscv_crc32c_h: + ID = Intrinsic::riscv_crc32c_h; + IntrinsicTypes = {ResultType}; + break; + case RISCV::BI__builtin_riscv_crc32c_w: + ID = Intrinsic::riscv_crc32c_w; + IntrinsicTypes = {ResultType}; + break; + case RISCV::BI__builtin_riscv_crc32c_d: + ID = Intrinsic::riscv_crc32c_d; + IntrinsicTypes = {ResultType}; + break; + default: { + llvm_unreachable("unexpected builtin ID"); + return nullptr; + } // default } assert(ID != Intrinsic::not_intrinsic); diff --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp index 305fcd574a373..a128fae78b9d0 100644 --- a/clang/lib/Sema/SemaChecking.cpp +++ b/clang/lib/Sema/SemaChecking.cpp @@ -3415,13 +3415,27 @@ bool Sema::CheckRISCVBuiltinFunctionCall(const TargetInfo &TI, CallExpr *TheCall) { // CodeGenFunction can also detect this, but this gives a better error // message. + bool FeatureMissing = false; + SmallVector<StringRef> ReqFeatures; StringRef Features = Context.BuiltinInfo.getRequiredFeatures(BuiltinID); - if (Features.find("experimental-v") != StringRef::npos && - !TI.hasFeature("experimental-v")) - return Diag(TheCall->getBeginLoc(), diag::err_riscvv_builtin_requires_v) - << TheCall->getSourceRange(); + Features.split(ReqFeatures, ','); - return false; + // Check if each required feature is included + for (auto &I : ReqFeatures) { + if (TI.hasFeature(I)) + continue; + // Make message like "experimental-zbr" to "Zbr" + I.consume_front("experimental-"); + std::string FeatureStr = I.str(); + FeatureStr[0] = std::toupper(FeatureStr[0]); + + // Error message + FeatureMissing = true; + Diag(TheCall->getBeginLoc(), diag::err_riscv_builtin_requires_extension) + << TheCall->getSourceRange() << StringRef(FeatureStr); + } + + return FeatureMissing; } bool Sema::CheckSystemZBuiltinFunctionCall(unsigned BuiltinID, diff --git a/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbr.c b/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbr.c new file mode 100644 index 0000000000000..f698f38dd1d3b --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbr.c @@ -0,0 +1,75 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py +// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-zbr -emit-llvm %s -o - \ +// RUN: | FileCheck %s -check-prefix=RV32ZBR + +// RV32ZBR-LABEL: @crc32_b( +// RV32ZBR-NEXT: entry: +// RV32ZBR-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// RV32ZBR-NEXT: store i32 [[A:%.*]], i32* [[A_ADDR]], align 4 +// RV32ZBR-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// RV32ZBR-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.crc32.b.i32(i32 [[TMP0]]) +// RV32ZBR-NEXT: ret i32 [[TMP1]] +// +long crc32_b(long a) { + return __builtin_riscv_crc32_b(a); +} + +// RV32ZBR-LABEL: @crc32_h( +// RV32ZBR-NEXT: entry: +// RV32ZBR-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// RV32ZBR-NEXT: store i32 [[A:%.*]], i32* [[A_ADDR]], align 4 +// RV32ZBR-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// RV32ZBR-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.crc32.h.i32(i32 [[TMP0]]) +// RV32ZBR-NEXT: ret i32 [[TMP1]] +// +long crc32_h(long a) { + return __builtin_riscv_crc32_h(a); +} + +// RV32ZBR-LABEL: @crc32_w( +// RV32ZBR-NEXT: entry: +// RV32ZBR-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// RV32ZBR-NEXT: store i32 [[A:%.*]], i32* [[A_ADDR]], align 4 +// RV32ZBR-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// RV32ZBR-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.crc32.w.i32(i32 [[TMP0]]) +// RV32ZBR-NEXT: ret i32 [[TMP1]] +// +long crc32_w(long a) { + return __builtin_riscv_crc32_w(a); +} + +// RV32ZBR-LABEL: @crc32c_b( +// RV32ZBR-NEXT: entry: +// RV32ZBR-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// RV32ZBR-NEXT: store i32 [[A:%.*]], i32* [[A_ADDR]], align 4 +// RV32ZBR-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// RV32ZBR-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.crc32c.b.i32(i32 [[TMP0]]) +// RV32ZBR-NEXT: ret i32 [[TMP1]] +// +long crc32c_b(long a) { + return __builtin_riscv_crc32c_b(a); +} + +// RV32ZBR-LABEL: @crc32c_h( +// RV32ZBR-NEXT: entry: +// RV32ZBR-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// RV32ZBR-NEXT: store i32 [[A:%.*]], i32* [[A_ADDR]], align 4 +// RV32ZBR-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// RV32ZBR-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.crc32c.h.i32(i32 [[TMP0]]) +// RV32ZBR-NEXT: ret i32 [[TMP1]] +// +long crc32c_h(long a) { + return __builtin_riscv_crc32c_h(a); +} + +// RV32ZBR-LABEL: @crc32c_w( +// RV32ZBR-NEXT: entry: +// RV32ZBR-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// RV32ZBR-NEXT: store i32 [[A:%.*]], i32* [[A_ADDR]], align 4 +// RV32ZBR-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// RV32ZBR-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.crc32c.w.i32(i32 [[TMP0]]) +// RV32ZBR-NEXT: ret i32 [[TMP1]] +// +long crc32c_w(long a) { + return __builtin_riscv_crc32c_w(a); +} diff --git a/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbr.c b/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbr.c new file mode 100644 index 0000000000000..5f9453b88add5 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbr.c @@ -0,0 +1,99 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zbr -emit-llvm %s -o - \ +// RUN: | FileCheck %s -check-prefix=RV64ZBR + +// RV64ZBR-LABEL: @crc32_b( +// RV64ZBR-NEXT: entry: +// RV64ZBR-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// RV64ZBR-NEXT: store i64 [[A:%.*]], i64* [[A_ADDR]], align 8 +// RV64ZBR-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8 +// RV64ZBR-NEXT: [[TMP1:%.*]] = call i64 @llvm.riscv.crc32.b.i64(i64 [[TMP0]]) +// RV64ZBR-NEXT: ret i64 [[TMP1]] +// +long crc32_b(long a) { + return __builtin_riscv_crc32_b(a); +} + +// RV64ZBR-LABEL: @crc32_h( +// RV64ZBR-NEXT: entry: +// RV64ZBR-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// RV64ZBR-NEXT: store i64 [[A:%.*]], i64* [[A_ADDR]], align 8 +// RV64ZBR-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8 +// RV64ZBR-NEXT: [[TMP1:%.*]] = call i64 @llvm.riscv.crc32.h.i64(i64 [[TMP0]]) +// RV64ZBR-NEXT: ret i64 [[TMP1]] +// +long crc32_h(long a) { + return __builtin_riscv_crc32_h(a); +} + +// RV64ZBR-LABEL: @crc32_w( +// RV64ZBR-NEXT: entry: +// RV64ZBR-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// RV64ZBR-NEXT: store i64 [[A:%.*]], i64* [[A_ADDR]], align 8 +// RV64ZBR-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8 +// RV64ZBR-NEXT: [[TMP1:%.*]] = call i64 @llvm.riscv.crc32.w.i64(i64 [[TMP0]]) +// RV64ZBR-NEXT: ret i64 [[TMP1]] +// +long crc32_w(long a) { + return __builtin_riscv_crc32_w(a); +} + +// RV64ZBR-LABEL: @crc32c_b( +// RV64ZBR-NEXT: entry: +// RV64ZBR-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// RV64ZBR-NEXT: store i64 [[A:%.*]], i64* [[A_ADDR]], align 8 +// RV64ZBR-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8 +// RV64ZBR-NEXT: [[TMP1:%.*]] = call i64 @llvm.riscv.crc32c.b.i64(i64 [[TMP0]]) +// RV64ZBR-NEXT: ret i64 [[TMP1]] +// +long crc32c_b(long a) { + return __builtin_riscv_crc32c_b(a); +} + +// RV64ZBR-LABEL: @crc32c_h( +// RV64ZBR-NEXT: entry: +// RV64ZBR-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// RV64ZBR-NEXT: store i64 [[A:%.*]], i64* [[A_ADDR]], align 8 +// RV64ZBR-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8 +// RV64ZBR-NEXT: [[TMP1:%.*]] = call i64 @llvm.riscv.crc32c.h.i64(i64 [[TMP0]]) +// RV64ZBR-NEXT: ret i64 [[TMP1]] +// +long crc32c_h(long a) { + return __builtin_riscv_crc32c_h(a); +} + +// RV64ZBR-LABEL: @crc32c_w( +// RV64ZBR-NEXT: entry: +// RV64ZBR-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// RV64ZBR-NEXT: store i64 [[A:%.*]], i64* [[A_ADDR]], align 8 +// RV64ZBR-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8 +// RV64ZBR-NEXT: [[TMP1:%.*]] = call i64 @llvm.riscv.crc32c.w.i64(i64 [[TMP0]]) +// RV64ZBR-NEXT: ret i64 [[TMP1]] +// +long crc32c_w(long a) { + return __builtin_riscv_crc32c_w(a); +} + +// RV64ZBR-LABEL: @crc32_d( +// RV64ZBR-NEXT: entry: +// RV64ZBR-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// RV64ZBR-NEXT: store i64 [[A:%.*]], i64* [[A_ADDR]], align 8 +// RV64ZBR-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8 +// RV64ZBR-NEXT: [[TMP1:%.*]] = call i64 @llvm.riscv.crc32.d.i64(i64 [[TMP0]]) +// RV64ZBR-NEXT: ret i64 [[TMP1]] +// +long crc32_d(long a) { + return __builtin_riscv_crc32_d(a); +} + +// RV64ZBR-LABEL: @crc32c_d( +// RV64ZBR-NEXT: entry: +// RV64ZBR-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// RV64ZBR-NEXT: store i64 [[A:%.*]], i64* [[A_ADDR]], align 8 +// RV64ZBR-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8 +// RV64ZBR-NEXT: [[TMP1:%.*]] = call i64 @llvm.riscv.crc32c.d.i64(i64 [[TMP0]]) +// RV64ZBR-NEXT: ret i64 [[TMP1]] +// +long crc32c_d(long a) { + return __builtin_riscv_crc32c_d(a); +} diff --git a/llvm/include/llvm/IR/IntrinsicsRISCV.td b/llvm/include/llvm/IR/IntrinsicsRISCV.td index bdb9725197975..0100fe5b8defd 100644 --- a/llvm/include/llvm/IR/IntrinsicsRISCV.td +++ b/llvm/include/llvm/IR/IntrinsicsRISCV.td @@ -10,6 +10,28 @@ // //===----------------------------------------------------------------------===// +//===----------------------------------------------------------------------===// +// RISC-V Bitmanip (Bit Manipulation) Extension +// Zbr extension part + +let TargetPrefix = "riscv" in { + + class BitMan_GPR_Intrinsics + : Intrinsic<[llvm_any_ty], + [LLVMMatchType<0>], + [IntrNoMem, IntrSpeculatable, IntrWillReturn]>; + + def int_riscv_crc32_b : BitMan_GPR_Intrinsics; + def int_riscv_crc32_h : BitMan_GPR_Intrinsics; + def int_riscv_crc32_w : BitMan_GPR_Intrinsics; + def int_riscv_crc32_d : BitMan_GPR_Intrinsics; + def int_riscv_crc32c_b : BitMan_GPR_Intrinsics; + def int_riscv_crc32c_h : BitMan_GPR_Intrinsics; + def int_riscv_crc32c_w : BitMan_GPR_Intrinsics; + def int_riscv_crc32c_d : BitMan_GPR_Intrinsics; + +} // TargetPrefix = "riscv" + //===----------------------------------------------------------------------===// // Atomics diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td index 68d5e7507633c..b6a4d2ea85fa2 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td @@ -819,6 +819,8 @@ def : InstAlias<"zext.b $rd, $rs", (ANDI GPR:$rd, GPR:$rs, 0xFF), 0>; /// Generic pattern classes +class PatGpr<SDPatternOperator OpNode, RVInst Inst> + : Pat<(OpNode GPR:$rs1), (Inst GPR:$rs1)>; class PatGprGpr<SDPatternOperator OpNode, RVInst Inst> : Pat<(OpNode GPR:$rs1, GPR:$rs2), (Inst GPR:$rs1, GPR:$rs2)>; class PatGprSimm12<SDPatternOperator OpNode, RVInstI Inst> diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoB.td b/llvm/lib/Target/RISCV/RISCVInstrInfoB.td index b9cc928cfbb70..365aef3b40512 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoB.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoB.td @@ -893,3 +893,17 @@ def : Pat<(i64 (or (and (assertsexti32 GPR:$rs2), 0xFFFFFFFFFFFF0000), (srl (and GPR:$rs1, 0xFFFFFFFF), (i64 16)))), (PACKUW GPR:$rs1, GPR:$rs2)>; } // Predicates = [HasStdExtZbp, IsRV64] + +let Predicates = [HasStdExtZbr] in { +def : PatGpr<int_riscv_crc32_b, CRC32B>; +def : PatGpr<int_riscv_crc32_h, CRC32H>; +def : PatGpr<int_riscv_crc32_w, CRC32W>; +def : PatGpr<int_riscv_crc32c_b, CRC32CB>; +def : PatGpr<int_riscv_crc32c_h, CRC32CH>; +def : PatGpr<int_riscv_crc32c_w, CRC32CW>; +} // Predicates = [HasStdExtZbr] + +let Predicates = [HasStdExtZbr, IsRV64] in { +def : PatGpr<int_riscv_crc32_d, CRC32D>; +def : PatGpr<int_riscv_crc32c_d, CRC32CD>; +} // Predicates = [HasStdExtZbr, IsRV64] diff --git a/llvm/test/CodeGen/RISCV/rv32zbr.ll b/llvm/test/CodeGen/RISCV/rv32zbr.ll new file mode 100644 index 0000000000000..d4f88990a01e9 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/rv32zbr.ll @@ -0,0 +1,69 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=riscv32 -mattr=experimental-zbr -verify-machineinstrs < %s \ +; RUN: | FileCheck %s -check-prefix=RV32ZBR + +declare i32 @llvm.riscv.crc32.b.i32(i32) + +define i32 @crc32b(i32 %a) nounwind { +; RV32ZBR-LABEL: crc32b: +; RV32ZBR: # %bb.0: +; RV32ZBR-NEXT: crc32.b a0, a0 +; RV32ZBR-NEXT: ret + %tmp = call i32 @llvm.riscv.crc32.b.i32(i32 %a) + ret i32 %tmp +} + +declare i32 @llvm.riscv.crc32.h.i32(i32) + +define i32 @crc32h(i32 %a) nounwind { +; RV32ZBR-LABEL: crc32h: +; RV32ZBR: # %bb.0: +; RV32ZBR-NEXT: crc32.h a0, a0 +; RV32ZBR-NEXT: ret + %tmp = call i32 @llvm.riscv.crc32.h.i32(i32 %a) + ret i32 %tmp +} + +declare i32 @llvm.riscv.crc32.w.i32(i32) + +define i32 @crc32w(i32 %a) nounwind { +; RV32ZBR-LABEL: crc32w: +; RV32ZBR: # %bb.0: +; RV32ZBR-NEXT: crc32.w a0, a0 +; RV32ZBR-NEXT: ret + %tmp = call i32 @llvm.riscv.crc32.w.i32(i32 %a) + ret i32 %tmp +} + +declare i32 @llvm.riscv.crc32c.b.i32(i32) + +define i32 @crc32cb(i32 %a) nounwind { +; RV32ZBR-LABEL: crc32cb: +; RV32ZBR: # %bb.0: +; RV32ZBR-NEXT: crc32c.b a0, a0 +; RV32ZBR-NEXT: ret + %tmp = call i32 @llvm.riscv.crc32c.b.i32(i32 %a) + ret i32 %tmp +} + +declare i32 @llvm.riscv.crc32c.h.i32(i32) + +define i32 @crc32ch(i32 %a) nounwind { +; RV32ZBR-LABEL: crc32ch: +; RV32ZBR: # %bb.0: +; RV32ZBR-NEXT: crc32c.h a0, a0 +; RV32ZBR-NEXT: ret + %tmp = call i32 @llvm.riscv.crc32c.h.i32(i32 %a) + ret i32 %tmp +} + +declare i32 @llvm.riscv.crc32c.w.i32(i32) + +define i32 @crc32cw(i32 %a) nounwind { +; RV32ZBR-LABEL: crc32cw: +; RV32ZBR: # %bb.0: +; RV32ZBR-NEXT: crc32c.w a0, a0 +; RV32ZBR-NEXT: ret + %tmp = call i32 @llvm.riscv.crc32c.w.i32(i32 %a) + ret i32 %tmp +} diff --git a/llvm/test/CodeGen/RISCV/rv64zbr.ll b/llvm/test/CodeGen/RISCV/rv64zbr.ll new file mode 100644 index 0000000000000..fadb2cb1e798a --- /dev/null +++ b/llvm/test/CodeGen/RISCV/rv64zbr.ll @@ -0,0 +1,91 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=riscv64 -mattr=experimental-zbr -verify-machineinstrs < %s \ +; RUN: | FileCheck %s -check-prefix=RV64ZBR + +declare i64 @llvm.riscv.crc32.b.i64(i64) + +define i64 @crc32b(i64 %a) nounwind { +; RV64ZBR-LABEL: crc32b: +; RV64ZBR: # %bb.0: +; RV64ZBR-NEXT: crc32.b a0, a0 +; RV64ZBR-NEXT: ret + %tmp = call i64 @llvm.riscv.crc32.b.i64(i64 %a) + ret i64 %tmp +} + +declare i64 @llvm.riscv.crc32.h.i64(i64) + +define i64 @crc32h(i64 %a) nounwind { +; RV64ZBR-LABEL: crc32h: +; RV64ZBR: # %bb.0: +; RV64ZBR-NEXT: crc32.h a0, a0 +; RV64ZBR-NEXT: ret + %tmp = call i64 @llvm.riscv.crc32.h.i64(i64 %a) + ret i64 %tmp +} + +declare i64 @llvm.riscv.crc32.w.i64(i64) + +define i64 @crc32w(i64 %a) nounwind { +; RV64ZBR-LABEL: crc32w: +; RV64ZBR: # %bb.0: +; RV64ZBR-NEXT: crc32.w a0, a0 +; RV64ZBR-NEXT: ret + %tmp = call i64 @llvm.riscv.crc32.w.i64(i64 %a) + ret i64 %tmp +} + +declare i64 @llvm.riscv.crc32c.b.i64(i64) + +define i64 @crc32cb(i64 %a) nounwind { +; RV64ZBR-LABEL: crc32cb: +; RV64ZBR: # %bb.0: +; RV64ZBR-NEXT: crc32c.b a0, a0 +; RV64ZBR-NEXT: ret + %tmp = call i64 @llvm.riscv.crc32c.b.i64(i64 %a) + ret i64 %tmp +} + +declare i64 @llvm.riscv.crc32c.h.i64(i64) + +define i64 @crc32ch(i64 %a) nounwind { +; RV64ZBR-LABEL: crc32ch: +; RV64ZBR: # %bb.0: +; RV64ZBR-NEXT: crc32c.h a0, a0 +; RV64ZBR-NEXT: ret + %tmp = call i64 @llvm.riscv.crc32c.h.i64(i64 %a) + ret i64 %tmp +} + +declare i64 @llvm.riscv.crc32c.w.i64(i64) + +define i64 @crc32cw(i64 %a) nounwind { +; RV64ZBR-LABEL: crc32cw: +; RV64ZBR: # %bb.0: +; RV64ZBR-NEXT: crc32c.w a0, a0 +; RV64ZBR-NEXT: ret + %tmp = call i64 @llvm.riscv.crc32c.w.i64(i64 %a) + ret i64 %tmp +} + +declare i64 @llvm.riscv.crc32.d.i64(i64) + +define i64 @crc32d(i64 %a) nounwind { +; RV64ZBR-LABEL: crc32d: +; RV64ZBR: # %bb.0: +; RV64ZBR-NEXT: crc32.d a0, a0 +; RV64ZBR-NEXT: ret + %tmp = call i64 @llvm.riscv.crc32.d.i64(i64 %a) + ret i64 %tmp +} + +declare i64 @llvm.riscv.crc32c.d.i64(i64) + +define i64 @crc32cd(i64 %a) nounwind { +; RV64ZBR-LABEL: crc32cd: +; RV64ZBR: # %bb.0: +; RV64ZBR-NEXT: crc32c.d a0, a0 +; RV64ZBR-NEXT: ret + %tmp = call i64 @llvm.riscv.crc32c.d.i64(i64 %a) + ret i64 %tmp +} _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits