craig.topper added inline comments.
================ Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoB.td:33 def riscv_shfl : SDNode<"RISCVISD::SHFL", SDTIntBinOp>; +def riscv_shflw : SDNode<"RISCVISD::SHFLW", SDT_RISCVIntBinOpW>; +def riscv_unshfl : SDNode<"RISCVISD::UNSHFL", SDTIntBinOp>; ---------------- Line the colons up ================ Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoB.td:749 def : PatGprImm<riscv_gorc, GORCI, uimmlog2xlen>; +def : PatGprImm<riscv_unshfl, UNSHFLI, shfl_uimm>; } // Predicates = [HasStdExtZbp] ---------------- Put this between riscv_shfl and riscv_grev so that shfl and unshfl are together ================ Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoB.td:946 +let Predicates = [HasStdExtZbp] in { +def : PatGprGpr<riscv_grev, GREV>; +def : PatGprGpr<riscv_gorc, GORC>; ---------------- Put these in the same block that has PatGprImm<riscv_grev ================ Comment at: llvm/test/CodeGen/RISCV/rv32zbp-intrinsic.ll:92 +; RV32IB: # %bb.0: +; RV32IB-NEXT: addi a1, zero, 29 +; RV32IB-NEXT: shfl a0, a0, a1 ---------------- This immediate is too large to make shfli. It needs to b 4 bits for i32. ================ Comment at: llvm/test/CodeGen/RISCV/rv32zbp-intrinsic.ll:126 +; RV32IB: # %bb.0: +; RV32IB-NEXT: addi a1, zero, 29 +; RV32IB-NEXT: unshfl a0, a0, a1 ---------------- Same here ================ Comment at: llvm/test/MC/RISCV/rv32b-aliases-valid.s:256 +# CHECK-S-OBJ: shfli t0, t1, 29 +shfl x5, x6, 29 + ---------------- This test fails check-llvm because 29 isn't a shfl_uimm on RV32 Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D100830/new/ https://reviews.llvm.org/D100830 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits