yaxunl updated this revision to Diff 339092. yaxunl marked 3 inline comments as done. yaxunl added a comment.
revised by Matt's comments CHANGES SINCE LAST ACTION https://reviews.llvm.org/D77013/new/ https://reviews.llvm.org/D77013 Files: clang/include/clang/Basic/CodeGenOptions.def clang/include/clang/Basic/DiagnosticDriverKinds.td clang/include/clang/Driver/Options.td clang/lib/CodeGen/TargetInfo.cpp clang/lib/Frontend/CompilerInvocation.cpp clang/test/CodeGenOpenCL/amdgpu-ieee.cl
Index: clang/test/CodeGenOpenCL/amdgpu-ieee.cl =================================================================== --- /dev/null +++ clang/test/CodeGenOpenCL/amdgpu-ieee.cl @@ -0,0 +1,47 @@ +// REQUIRES: amdgpu-registered-target +// +// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa -O0 -emit-llvm -o - %s \ +// RUN: | FileCheck -check-prefixes=COMMON,ON %s +// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa -O0 -emit-llvm -o - %s \ +// RUN: -mno-amdgpu-ieee -menable-no-nans \ +// RUN: | FileCheck -check-prefixes=COMMON,OFF %s +// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa -O0 -emit-llvm -o - %s \ +// RUN: -mno-amdgpu-ieee -cl-fast-relaxed-math \ +// RUN: | FileCheck -check-prefixes=COMMON,OFF %s + +// Check AMDGCN ISA generation. + +// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa -O3 -S -o - %s \ +// RUN: | FileCheck -check-prefixes=ISA-ON %s +// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa -O3 -S -o - %s \ +// RUN: -mno-amdgpu-ieee -menable-no-nans \ +// RUN: | FileCheck -check-prefixes=ISA-OFF %s + +// Check diagnostics when using -mno-amdgpu-ieee without NoHonorNaNs. + +// RUN: not %clang_cc1 -triple amdgcn-amd-amdhsa -O0 -emit-llvm -o - %s \ +// RUN: -mno-amdgpu-ieee 2>&1 | FileCheck -check-prefixes=DIAG %s + +// COMMON: define{{.*}} amdgpu_kernel void @kern{{.*}} [[ATTRS1:#[0-9]+]] +// ISA-ON: v_mul_f32_e64 v{{[0-9]+}}, 1.0, s{{[0-9]+}} +// ISA-ON: v_mul_f32_e64 v{{[0-9]+}}, 1.0, s{{[0-9]+}} +// ISA-ON: v_min_f32_e32 +// ISA-ON: ; IeeeMode: 1 +// ISA-OFF-NOT: v_mul_f32_e64 v{{[0-9]+}}, 1.0, s{{[0-9]+}} +// ISA-OFF-NOT: v_mul_f32_e64 v{{[0-9]+}}, 1.0, s{{[0-9]+}} +// ISA-OFF: v_min_f32_e32 +// ISA-OFF: ; IeeeMode: 0 +kernel void kern(global float *x, float y, float z) { + *x = __builtin_fmin(y, z); +} + +// COMMON: define{{.*}}void @fun() [[ATTRS2:#[0-9]+]] +void fun() { +} + +// ON-NOT: attributes [[ATTRS1]] = {{.*}} "amdgpu-ieee" +// OFF: attributes [[ATTRS1]] = {{.*}} "amdgpu-ieee"="false"{{.*}}"no-nans-fp-math"="true"{{.*}}"no-trapping-math"="true" +// ON-NOT: attributes [[ATTRS2]] = {{.*}} "amdgpu-ieee" +// OFF: attributes [[ATTRS2]] = {{.*}} "amdgpu-ieee"="false"{{.*}}"no-nans-fp-math"="true"{{.*}}"no-trapping-math"="true" + +// DIAG: invalid argument '-mno-amdgpu-ieee' only allowed with floating point options which do not honor NaNs, e.g. '-fno-honor-nans', '-ffast-math', '-ffinite-math-only', etc. Index: clang/lib/Frontend/CompilerInvocation.cpp =================================================================== --- clang/lib/Frontend/CompilerInvocation.cpp +++ clang/lib/Frontend/CompilerInvocation.cpp @@ -1943,6 +1943,11 @@ else if (Args.hasArg(options::OPT_fno_finite_loops)) Opts.FiniteLoops = CodeGenOptions::FiniteLoopsKind::Never; + Opts.EmitIEEENaNCompliantInsts = + Args.hasFlag(options::OPT_mamdgpu_ieee, options::OPT_mno_amdgpu_ieee); + if (!Opts.EmitIEEENaNCompliantInsts && !LangOptsRef.NoHonorNaNs) + Diags.Report(diag::err_drv_amdgpu_ieee_without_no_honor_nans); + return Diags.getNumErrors() == NumErrorsBefore; } Index: clang/lib/CodeGen/TargetInfo.cpp =================================================================== --- clang/lib/CodeGen/TargetInfo.cpp +++ clang/lib/CodeGen/TargetInfo.cpp @@ -9166,6 +9166,9 @@ if (M.getContext().getTargetInfo().allowAMDGPUUnsafeFPAtomics()) F->addFnAttr("amdgpu-unsafe-fp-atomics", "true"); + + if (!getABIInfo().getCodeGenOpts().EmitIEEENaNCompliantInsts) + F->addFnAttr("amdgpu-ieee", "false"); } unsigned AMDGPUTargetCodeGenInfo::getOpenCLKernelCallingConv() const { Index: clang/include/clang/Driver/Options.td =================================================================== --- clang/include/clang/Driver/Options.td +++ clang/include/clang/Driver/Options.td @@ -3171,6 +3171,14 @@ Values<"command,reactor">, HelpText<"Execution model (WebAssembly only)">; +defm amdgpu_ieee : BoolOption<"m", "amdgpu-ieee", + CodeGenOpts<"EmitIEEENaNCompliantInsts">, DefaultTrue, + PosFlag<SetTrue, [], "Sets the IEEE bit in the expected default floating point " + " mode register. Floating point opcodes that support exception flag " + "gathering quiet and propagate signaling NaN inputs per IEEE 754-2008 " + "(AMDGPU only)">, + NegFlag<SetFalse, [CC1Option]>>, Group<m_Group>; + def mcode_object_version_EQ : Joined<["-"], "mcode-object-version=">, Group<m_Group>, HelpText<"Specify code object ABI version. Defaults to 3. (AMDGPU only)">, MetaVarName<"<version>">, Values<"2,3,4">; Index: clang/include/clang/Basic/DiagnosticDriverKinds.td =================================================================== --- clang/include/clang/Basic/DiagnosticDriverKinds.td +++ clang/include/clang/Basic/DiagnosticDriverKinds.td @@ -127,6 +127,10 @@ "invalid -Xopenmp-target argument: '%0', options requiring arguments are unsupported">; def err_drv_argument_only_allowed_with : Error< "invalid argument '%0' only allowed with '%1'">; +def err_drv_amdgpu_ieee_without_no_honor_nans : Error< + "invalid argument '-mno-amdgpu-ieee' only allowed with floating point options " + "which do not honor NaNs, e.g. '-fno-honor-nans', '-ffast-math', " + "'-ffinite-math-only', etc.">; def err_drv_argument_not_allowed_with : Error< "invalid argument '%0' not allowed with '%1'">; def err_drv_invalid_version_number : Error< Index: clang/include/clang/Basic/CodeGenOptions.def =================================================================== --- clang/include/clang/Basic/CodeGenOptions.def +++ clang/include/clang/Basic/CodeGenOptions.def @@ -425,6 +425,11 @@ /// according to the field declaring type width. CODEGENOPT(AAPCSBitfieldWidth, 1, 1) +/// Sets the IEEE bit in the expected default floating point mode register. +/// Floating point opcodes that support exception flag gathering quiet and +/// propagate signaling NaN inputs per IEEE 754-2008 (AMDGPU Only) +CODEGENOPT(EmitIEEENaNCompliantInsts, 1, 1) + #undef CODEGENOPT #undef ENUM_CODEGENOPT #undef VALUE_CODEGENOPT
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