lhames added a comment. In D96033#2757930 <https://reviews.llvm.org/D96033#2757930>, @hubert.reinterpretcast wrote:
> ... > Command Output (stderr): > > triple: powerpc64-ibm-aix7.2.0.0 > datalayout: E-m:a-i64:64-n32:64-S128-v256:256:256-v512:512:512 > error: Added modules have incompatible data layouts: > e-m:e-i64:64-n32:64-S128-v256:256:256-v512:512:512 (module) vs > E-m:a-i64:64-n32:64-S128-v256:256:256-v512:512:512 (jit) Thanks @hubert.reinterpretcast! Ok, looks like the JIT is getting the layout right, but clang-repl is constructing a module with an little-endian layout for some reason. I'm not sure why that would be but it's probably a question for @v.g.vassilev tomorrow. In the mean time I have conditionally disabled this test on ppc64 in 71a0609a2b <https://reviews.llvm.org/rG71a0609a2b533dbcd6826ad774b6bee5e9818644>. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D96033/new/ https://reviews.llvm.org/D96033 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
