NoQ added a comment.
WDYT about the following format:
Equality constraints:
reg_$0<a> == reg_$1<b>
== reg_$2<c>
Disequality constraints:
reg_$0<a> != reg_$3<d>,
!= reg_$4<e>
Comma is a bit hard to notice but otherwise kinda nicely readable?
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D104917/new/
https://reviews.llvm.org/D104917
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