Author: kparzysz Date: Wed May 18 09:56:14 2016 New Revision: 269934 URL: http://llvm.org/viewvc/llvm-project?rev=269934&view=rev Log: [Hexagon] Recognize "q" and "v" in inline-asm as register constraints
Clang follow-up to r269933. Added: cfe/trunk/test/CodeGen/hexagon-inline-asm.c Modified: cfe/trunk/lib/Basic/Targets.cpp Modified: cfe/trunk/lib/Basic/Targets.cpp URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Basic/Targets.cpp?rev=269934&r1=269933&r2=269934&view=diff ============================================================================== --- cfe/trunk/lib/Basic/Targets.cpp (original) +++ cfe/trunk/lib/Basic/Targets.cpp Wed May 18 09:56:14 2016 @@ -6016,7 +6016,16 @@ public: bool validateAsmConstraint(const char *&Name, TargetInfo::ConstraintInfo &Info) const override { - return true; + switch (*Name) { + case 'v': + case 'q': + if (HasHVX) { + Info.setAllowsRegister(); + return true; + } + break; + } + return false; } void getTargetDefines(const LangOptions &Opts, Added: cfe/trunk/test/CodeGen/hexagon-inline-asm.c URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/hexagon-inline-asm.c?rev=269934&view=auto ============================================================================== --- cfe/trunk/test/CodeGen/hexagon-inline-asm.c (added) +++ cfe/trunk/test/CodeGen/hexagon-inline-asm.c Wed May 18 09:56:14 2016 @@ -0,0 +1,11 @@ +// RUN: %clang_cc1 -triple hexagon-unknown-elf -target-feature +hvx -emit-llvm -o - %s | FileCheck %s + +typedef int v64 __attribute__((__vector_size__(64))) + __attribute__((aligned(64))); + +void foo(v64 v0, v64 v1, v64 *p) { + v64 q0; + asm ("%0 = vgtw(%1.w,%2.w)" : "=q"(q0) : "v"(v0), "v"(v1)); +// CHECK: call <16 x i32> asm "$0 = vgtw($1.w,$2.w)", "=q,v,v"(<16 x i32>{{.*}}, <16 x i32>{{.*}}) + *p = q0; +} _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits