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An extra test case added for the builtin __LDARX.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D105926
Files:
clang/test/CodeGen/builtins-ppc-xlcompat-check-ldarx-opt.ll
Index: clang/test/CodeGen/builtins-ppc-xlcompat-check-ldarx-opt.ll
===================================================================
--- /dev/null
+++ clang/test/CodeGen/builtins-ppc-xlcompat-check-ldarx-opt.ll
@@ -0,0 +1,160 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN: -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN: -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN: -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-AIX
+
+; Function Attrs: noinline nounwind optnone uwtable
+define dso_local signext i32 @main() #0 {
+; CHECK-LABEL: main:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: li 3, 0
+; CHECK-NEXT: stw 3, -12(1)
+; CHECK-NEXT: li 3, -1
+; CHECK-NEXT: std 3, -32(1)
+; CHECK-NEXT: li 3, 0
+; CHECK-NEXT: std 3, -40(1)
+; CHECK-NEXT: .LBB0_1: # %do.body
+; CHECK-NEXT: #
+; CHECK-NEXT: addi 3, 1, -32
+; CHECK-NEXT: #APP
+; CHECK-NEXT: ldarx 3, 0, 3
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: std 3, -24(1)
+; CHECK-NEXT: addi 3, 1, -32
+; CHECK-NEXT: ld 4, -24(1)
+; CHECK-NEXT: ld 5, -40(1)
+; CHECK-NEXT: and 4, 4, 5
+; CHECK-NEXT: stdcx. 4, 0, 3
+; CHECK-NEXT: mfocrf 3, 128
+; CHECK-NEXT: srwi 3, 3, 28
+; CHECK-NEXT: stw 3, -44(1)
+; CHECK-NEXT: # %bb.2: # %do.cond
+; CHECK-NEXT: #
+; CHECK-NEXT: lwz 3, -44(1)
+; CHECK-NEXT: cmplwi 3, 0
+; CHECK-NEXT: beq 0, .LBB0_1
+; CHECK-NEXT: b .LBB0_3
+; CHECK-NEXT: .LBB0_3: # %do.end
+; CHECK-NEXT: ld 3, -32(1)
+; CHECK-NEXT: cmpdi 3, 0
+; CHECK-NEXT: bne 0, .LBB0_5
+; CHECK-NEXT: # %bb.4: # %if.then
+; CHECK-NEXT: li 3, 55
+; CHECK-NEXT: stw 3, -12(1)
+; CHECK-NEXT: b .LBB0_6
+; CHECK-NEXT: .LBB0_5: # %if.end
+; CHECK-NEXT: li 3, 66
+; CHECK-NEXT: stw 3, -12(1)
+; CHECK-NEXT: .LBB0_6: # %return
+; CHECK-NEXT: lwa 3, -12(1)
+; CHECK-NEXT: blr
+;
+; CHECK-AIX-LABEL: main:
+; CHECK-AIX: # %bb.0: # %entry
+; CHECK-AIX-NEXT: li 3, 0
+; CHECK-AIX-NEXT: stw 3, -12(1)
+; CHECK-AIX-NEXT: li 4, -1
+; CHECK-AIX-NEXT: std 4, -32(1)
+; CHECK-AIX-NEXT: std 3, -40(1)
+; CHECK-AIX-NEXT: b L..BB0_1
+; CHECK-AIX-NEXT: L..BB0_1: # %do.body
+; CHECK-AIX-NEXT: #
+; CHECK-AIX-NEXT: addi 3, 1, -32
+; CHECK-AIX-NEXT: #APP
+; CHECK-AIX-NEXT: ldarx 4, 0, 3
+; CHECK-AIX-NEXT: #NO_APP
+; CHECK-AIX-NEXT: std 4, -24(1)
+; CHECK-AIX-NEXT: ld 4, -24(1)
+; CHECK-AIX-NEXT: ld 5, -40(1)
+; CHECK-AIX-NEXT: and 4, 4, 5
+; CHECK-AIX-NEXT: stdcx. 4, 0, 3
+; CHECK-AIX-NEXT: mfocrf 3, 128
+; CHECK-AIX-NEXT: srwi 3, 3, 28
+; CHECK-AIX-NEXT: stw 3, -44(1)
+; CHECK-AIX-NEXT: b L..BB0_2
+; CHECK-AIX-NEXT: L..BB0_2: # %do.cond
+; CHECK-AIX-NEXT: #
+; CHECK-AIX-NEXT: lwz 3, -44(1)
+; CHECK-AIX-NEXT: cmplwi 3, 0
+; CHECK-AIX-NEXT: beq 0, L..BB0_1
+; CHECK-AIX-NEXT: b L..BB0_3
+; CHECK-AIX-NEXT: L..BB0_3: # %do.end
+; CHECK-AIX-NEXT: ld 3, -32(1)
+; CHECK-AIX-NEXT: cmpldi 3, 0
+; CHECK-AIX-NEXT: bne 0, L..BB0_5
+; CHECK-AIX-NEXT: b L..BB0_4
+; CHECK-AIX-NEXT: L..BB0_4: # %if.then
+; CHECK-AIX-NEXT: li 3, 55
+; CHECK-AIX-NEXT: stw 3, -12(1)
+; CHECK-AIX-NEXT: b L..BB0_6
+; CHECK-AIX-NEXT: L..BB0_5: # %if.end
+; CHECK-AIX-NEXT: li 3, 66
+; CHECK-AIX-NEXT: stw 3, -12(1)
+; CHECK-AIX-NEXT: b L..BB0_6
+; CHECK-AIX-NEXT: L..BB0_6: # %return
+; CHECK-AIX-NEXT: lwa 3, -12(1)
+; CHECK-AIX-NEXT: blr
+entry:
+ %retval = alloca i32, align 4
+ %x = alloca i64, align 8
+ %x64 = alloca i64, align 8
+ %andval = alloca i64, align 8
+ %k = alloca i32, align 4
+ store i32 0, i32* %retval, align 4
+ store i64 -1, i64* %x64, align 8
+ store i64 0, i64* %andval, align 8
+ br label %do.body
+
+do.body: ; preds = %do.cond, %entry
+ %0 = call i64 asm sideeffect "ldarx $0, ${1:y}", "=r,*Z,~{memory}"(i64* %x64)
+ store i64 %0, i64* %x, align 8
+ %1 = bitcast i64* %x64 to i8*
+ %2 = load i64, i64* %x, align 8
+ %3 = load i64, i64* %andval, align 8
+ %and = and i64 %2, %3
+ %4 = call i32 @llvm.ppc.stdcx(i8* %1, i64 %and)
+ store i32 %4, i32* %k, align 4
+ br label %do.cond
+
+do.cond: ; preds = %do.body
+ %5 = load i32, i32* %k, align 4
+ %tobool = icmp ne i32 %5, 0
+ %lnot = xor i1 %tobool, true
+ br i1 %lnot, label %do.body, label %do.end, !llvm.loop !4
+
+do.end: ; preds = %do.cond
+ %6 = load i64, i64* %x64, align 8
+ %cmp = icmp eq i64 %6, 0
+ br i1 %cmp, label %if.then, label %if.end
+
+if.then: ; preds = %do.end
+ store i32 55, i32* %retval, align 4
+ br label %return
+
+if.end: ; preds = %do.end
+ store i32 66, i32* %retval, align 4
+ br label %return
+
+return: ; preds = %if.end, %if.then
+ %7 = load i32, i32* %retval, align 4
+ ret i32 %7
+}
+
+; Function Attrs: nounwind writeonly
+declare i32 @llvm.ppc.stdcx(i8*, i64) #1
+
+attributes #0 = { noinline nounwind optnone uwtable "frame-pointer"="all" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="ppc64le" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+htm,+isa-v207-instructions,+power8-vector,+vsx,-isa-v30-instructions,-power9-vector,-privileged,-rop-protect,-spe" }
+attributes #1 = { nounwind writeonly }
+
+!llvm.module.flags = !{!0, !1, !2}
+!llvm.ident = !{!3}
+
+!0 = !{i32 1, !"wchar_size", i32 4}
+!1 = !{i32 7, !"uwtable", i32 1}
+!2 = !{i32 7, !"frame-pointer", i32 2}
+!3 = !{!"clang version 13.0.0"}
+!4 = distinct !{!4, !5}
+!5 = !{!"llvm.loop.mustprogress"}
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