tlively added inline comments.
================ Comment at: llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td:324 + PatFrag<(ops node:$ptr, node:$vec, node:$idx), + (vector_insert $vec, (i32 (extloadi8 $ptr)), $idx)>; +def load16_lane : ---------------- aheejin wrote: > Why are i8 and i16 are extended-loaded? For i8x16 and i16x8 vectors, loading a lane from memory means loading just the i8 or i16. But after selection DAG legalization, the result of those loads are legalized to be i32, making these extending loads. If this were a DAG combine rather than an ISel pattern, I would use the pre-legalization i8 and i16 with non-extending loads. ================ Comment at: llvm/test/CodeGen/WebAssembly/simd-build-vector.ll:214 ; CHECK: v128.const $push[[L0:[0-9]+]]=, 0, 0, 0, 0, 42, 0, 0, 0, 0, 0, 0, 0, 0, 0, 42, 0 -; CHECK: i8x16.replace_lane +; CHECK: v128.load8_lane ; CHECK: i8x16.replace_lane ---------------- aheejin wrote: > Why the change? The lane for the swizzle comes from a load from the stack, so that now gets selected to v128.load8_lane rather than a load followed by a replace_lane. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D105950/new/ https://reviews.llvm.org/D105950 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
