craig.topper added inline comments.
================
Comment at: llvm/lib/Target/X86/X86ISelLowering.cpp:31087
+ // Now widen to 128 bits.
+ unsigned NumConcats = 128 / TmpVT.getSizeInBits();
+ MVT ConcatVT = MVT::getVectorVT(EleVT.getSimpleVT(), 8 * NumConcats);
----------------
LuoYuanke wrote:
> Is it possible the type is i3/i5/i7?
We should only get here for integer type that we enabled Custom handling for.
================
Comment at: llvm/lib/Target/X86/X86InstrAVX512.td:8194
+ }
+ def : InstAlias<OpcodeStr#"x\t{$src, $dst|$dst, $src}",
+ (!cast<Instruction>(NAME # "Z128rr") VR128X:$dst,
----------------
LuoYuanke wrote:
> What is the alias used for? Can't it be distinguished from operand?
The memory form can't be distinquished by operand and requires a suffix. This
alias exists so that the register form can also use a suffix even though it
isn't required. It allows an "rm" constraint to be used for a suffixed mnemonic
in inline assembly without needing to know if the compiler will pick register
or memory.
================
Comment at: llvm/lib/Target/X86/X86InstrAVX512.td:8193
+ defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v8f16x_info, v2f64x_info,
null_frag,
+ null_frag, sched.XMM, "{1to2}", "{x}", f128mem,
+ VK2WM>, EVEX_V128;
----------------
LuoYuanke wrote:
> Why null_frag instead of X86vfpround?
The masked forms require X86vmfpround and the unmasked forms require
X86any_vfpround. Template doesn't handle that. So there are extra patterns later
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D105265/new/
https://reviews.llvm.org/D105265
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