vhscampos updated this revision to Diff 372473. vhscampos marked 3 inline comments as done. vhscampos added a comment.
1. Enable the SVE2 extension as default. 2. Remove out of date comments in tests. 3. Remove unrelated change. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D109517/new/ https://reviews.llvm.org/D109517 Files: clang/lib/Basic/Targets/AArch64.cpp clang/lib/Basic/Targets/AArch64.h clang/lib/Basic/Targets/ARM.cpp clang/lib/Driver/ToolChains/Arch/AArch64.cpp clang/test/Driver/aarch64-cpus.c clang/test/Driver/arm-cortex-cpus.c clang/test/Preprocessor/aarch64-target-features.c clang/test/Preprocessor/arm-target-features.c llvm/include/llvm/ADT/Triple.h llvm/include/llvm/Support/AArch64TargetParser.def llvm/include/llvm/Support/ARMTargetParser.def llvm/lib/Support/AArch64TargetParser.cpp llvm/lib/Support/ARMTargetParser.cpp llvm/lib/Support/Triple.cpp llvm/lib/Target/AArch64/AArch64.td llvm/lib/Target/AArch64/AArch64InstrInfo.td llvm/lib/Target/AArch64/AArch64Subtarget.h llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp llvm/lib/Target/ARM/ARM.td llvm/lib/Target/ARM/ARMSubtarget.h llvm/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp llvm/test/MC/AArch64/SME/directives-negative.s llvm/test/MC/AArch64/SME/directives.s llvm/test/MC/AArch64/SVE2/directive-arch-negative.s llvm/test/MC/AArch64/SVE2/directive-arch.s llvm/unittests/Support/TargetParserTest.cpp
Index: llvm/unittests/Support/TargetParserTest.cpp =================================================================== --- llvm/unittests/Support/TargetParserTest.cpp +++ llvm/unittests/Support/TargetParserTest.cpp @@ -31,6 +31,7 @@ "armv8.5a", "armv8.6-a", "armv8.6a", "armv8.7-a", "armv8.7a", "armv8-r", "armv8r", "armv8-m.base","armv8m.base", "armv8-m.main", "armv8m.main", "iwmmxt", "iwmmxt2", "xscale", "armv8.1-m.main", + "armv9-a", "armv9.1-a", "armv9.2-a", }; template <ARM::ISAKind ISAKind> @@ -492,6 +493,15 @@ EXPECT_TRUE( testARMArch("armv8.7-a", "generic", "v8.7a", ARMBuildAttrs::CPUArch::v8_A)); + EXPECT_TRUE( + testARMArch("armv9-a", "generic", "v9a", + ARMBuildAttrs::CPUArch::v8_A)); + EXPECT_TRUE( + testARMArch("armv9.1-a", "generic", "v9.1a", + ARMBuildAttrs::CPUArch::v8_A)); + EXPECT_TRUE( + testARMArch("armv9.2-a", "generic", "v9.2a", + ARMBuildAttrs::CPUArch::v8_A)); EXPECT_TRUE( testARMArch("armv8-r", "cortex-r52", "v8r", ARMBuildAttrs::CPUArch::v8_R)); @@ -821,6 +831,9 @@ case ARM::ArchKind::ARMV8_5A: case ARM::ArchKind::ARMV8_6A: case ARM::ArchKind::ARMV8_7A: + case ARM::ArchKind::ARMV9A: + case ARM::ArchKind::ARMV9_1A: + case ARM::ArchKind::ARMV9_2A: EXPECT_EQ(ARM::ProfileKind::A, ARM::parseArchProfile(ARMArch[i])); break; default: @@ -1204,6 +1217,12 @@ ARMBuildAttrs::CPUArch::v8_A)); EXPECT_TRUE(testAArch64Arch("armv8.7-a", "generic", "v8.7a", ARMBuildAttrs::CPUArch::v8_A)); + EXPECT_TRUE(testAArch64Arch("armv9-a", "generic", "v9a", + ARMBuildAttrs::CPUArch::v8_A)); + EXPECT_TRUE(testAArch64Arch("armv9.1-a", "generic", "v9.1a", + ARMBuildAttrs::CPUArch::v8_A)); + EXPECT_TRUE(testAArch64Arch("armv9.2-a", "generic", "v9.2a", + ARMBuildAttrs::CPUArch::v8_A)); } bool testAArch64Extension(StringRef CPUName, AArch64::ArchKind AK, Index: llvm/test/MC/AArch64/SVE2/directive-arch.s =================================================================== --- llvm/test/MC/AArch64/SVE2/directive-arch.s +++ llvm/test/MC/AArch64/SVE2/directive-arch.s @@ -1,21 +1,21 @@ // RUN: llvm-mc -triple aarch64 -filetype asm -o - %s 2>&1 | FileCheck %s -.arch armv8-a+sve2 +.arch armv9-a+sve2 tbx z0.b, z1.b, z2.b // CHECK: tbx z0.b, z1.b, z2.b -.arch armv8-a+sve2-aes +.arch armv9-a+sve2-aes aesd z23.b, z23.b, z13.b // CHECK: aesd z23.b, z23.b, z13.b -.arch armv8-a+sve2-sm4 +.arch armv9-a+sve2-sm4 sm4e z0.s, z0.s, z0.s // CHECK: sm4e z0.s, z0.s, z0.s -.arch armv8-a+sve2-sha3 +.arch armv9-a+sve2-sha3 rax1 z0.d, z0.d, z0.d // CHECK: rax1 z0.d, z0.d, z0.d -.arch armv8-a+sve2-bitperm +.arch armv9-a+sve2-bitperm bgrp z21.s, z10.s, z21.s // CHECK: bgrp z21.s, z10.s, z21.s Index: llvm/test/MC/AArch64/SVE2/directive-arch-negative.s =================================================================== --- llvm/test/MC/AArch64/SVE2/directive-arch-negative.s +++ llvm/test/MC/AArch64/SVE2/directive-arch-negative.s @@ -1,31 +1,31 @@ // RUN: not llvm-mc -triple aarch64 -filetype asm -o - %s 2>&1 | FileCheck %s -.arch armv8-a+sve2 -.arch armv8-a+nosve2 +.arch armv9-a+sve2 +.arch armv9-a+nosve2 tbx z0.b, z1.b, z2.b // CHECK: error: instruction requires: streaming-sve or sve2 // CHECK-NEXT: tbx z0.b, z1.b, z2.b -.arch armv8-a+sve2-aes -.arch armv8-a+nosve2-aes +.arch armv9-a+sve2-aes +.arch armv9-a+nosve2-aes aesd z23.b, z23.b, z13.b // CHECK: error: instruction requires: sve2-aes // CHECK-NEXT: aesd z23.b, z23.b, z13.b -.arch armv8-a+sve2-sm4 -.arch armv8-a+nosve2-sm4 +.arch armv9-a+sve2-sm4 +.arch armv9-a+nosve2-sm4 sm4e z0.s, z0.s, z0.s // CHECK: error: instruction requires: sve2-sm4 // CHECK-NEXT: sm4e z0.s, z0.s, z0.s -.arch armv8-a+sve2-sha3 -.arch armv8-a+nosve2-sha3 +.arch armv9-a+sve2-sha3 +.arch armv9-a+nosve2-sha3 rax1 z0.d, z0.d, z0.d // CHECK: error: instruction requires: sve2-sha3 // CHECK-NEXT: rax1 z0.d, z0.d, z0.d -.arch armv8-a+sve2-bitperm -.arch armv8-a+nosve2-bitperm +.arch armv9-a+sve2-bitperm +.arch armv9-a+nosve2-bitperm bgrp z21.s, z10.s, z21.s // CHECK: error: instruction requires: sve2-bitperm // CHECK-NEXT: bgrp z21.s, z10.s, z21.s Index: llvm/test/MC/AArch64/SME/directives.s =================================================================== --- llvm/test/MC/AArch64/SME/directives.s +++ llvm/test/MC/AArch64/SME/directives.s @@ -18,18 +18,18 @@ .arch_extension nosme-i64 -.arch armv8-a+sme +.arch armv9-a+sme smstart // CHECK: smstart -.arch armv8-a+nosme +.arch armv9-a+nosme -.arch armv8-a+sme-f64 +.arch armv9-a+sme-f64 fmopa za0.d, p0/m, p0/m, z0.d, z0.d // CHECK: fmopa za0.d, p0/m, p0/m, z0.d, z0.d -.arch armv8-a+nosme-f64 +.arch armv9-a+nosme-f64 -.arch armv8-a+sme-i64 +.arch armv9-a+sme-i64 addha za0.d, p0/m, p0/m, z0.d // CHECK: addha za0.d, p0/m, p0/m, z0.d Index: llvm/test/MC/AArch64/SME/directives-negative.s =================================================================== --- llvm/test/MC/AArch64/SME/directives-negative.s +++ llvm/test/MC/AArch64/SME/directives-negative.s @@ -18,20 +18,20 @@ // CHECK: error: instruction requires: sme-i64 // CHECK-NEXT: addha za0.d, p0/m, p0/m, z0.d -.arch armv8-a+sme -.arch armv8-a+nosme +.arch armv9-a+sme +.arch armv9-a+nosme smstart // CHECK: error: instruction requires: sme // CHECK-NEXT: smstart -.arch armv8-a+sme-f64 -.arch armv8-a+nosme-f64 +.arch armv9-a+sme-f64 +.arch armv9-a+nosme-f64 fmopa za0.d, p0/m, p0/m, z0.d, z0.d // CHECK: error: instruction requires: sme-f64 // CHECK-NEXT: fmopa za0.d, p0/m, p0/m, z0.d, z0.d -.arch armv8-a+sme-i64 -.arch armv8-a+nosme-i64 +.arch armv9-a+sme-i64 +.arch armv9-a+nosme-i64 addha za0.d, p0/m, p0/m, z0.d // CHECK: error: instruction requires: sme-i64 // CHECK-NEXT: addha za0.d, p0/m, p0/m, z0.d Index: llvm/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp =================================================================== --- llvm/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp +++ llvm/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp @@ -785,6 +785,9 @@ case ARM::ArchKind::ARMV8_4A: case ARM::ArchKind::ARMV8_5A: case ARM::ArchKind::ARMV8_6A: + case ARM::ArchKind::ARMV9A: + case ARM::ArchKind::ARMV9_1A: + case ARM::ArchKind::ARMV9_2A: S.setAttributeItem(CPU_arch_profile, ApplicationProfile, false); S.setAttributeItem(ARM_ISA_use, Allowed, false); S.setAttributeItem(THUMB_ISA_use, AllowThumb32, false); Index: llvm/lib/Target/ARM/ARMSubtarget.h =================================================================== --- llvm/lib/Target/ARM/ARMSubtarget.h +++ llvm/lib/Target/ARM/ARMSubtarget.h @@ -124,6 +124,9 @@ ARMv8mMainline, ARMv8r, ARMv81mMainline, + ARMv9a, + ARMv91a, + ARMv92a, }; public: @@ -170,6 +173,9 @@ bool HasV8_5aOps = false; bool HasV8_6aOps = false; bool HasV8_7aOps = false; + bool HasV9_0aOps = false; + bool HasV9_1aOps = false; + bool HasV9_2aOps = false; bool HasV8MBaselineOps = false; bool HasV8MMainlineOps = false; bool HasV8_1MMainlineOps = false; @@ -618,6 +624,9 @@ bool hasV8_5aOps() const { return HasV8_5aOps; } bool hasV8_6aOps() const { return HasV8_6aOps; } bool hasV8_7aOps() const { return HasV8_7aOps; } + bool hasV9_0aOps() const { return HasV9_0aOps; } + bool hasV9_1aOps() const { return HasV9_1aOps; } + bool hasV9_2aOps() const { return HasV9_2aOps; } bool hasV8MBaselineOps() const { return HasV8MBaselineOps; } bool hasV8MMainlineOps() const { return HasV8MMainlineOps; } bool hasV8_1MMainlineOps() const { return HasV8_1MMainlineOps; } Index: llvm/lib/Target/ARM/ARM.td =================================================================== --- llvm/lib/Target/ARM/ARM.td +++ llvm/lib/Target/ARM/ARM.td @@ -539,6 +539,18 @@ "Support ARM v8.7a instructions", [HasV8_6aOps]>; +def HasV9_0aOps : SubtargetFeature<"v9a", "HasV9_0aOps", "true", + "Support ARM v9a instructions", + [HasV8_5aOps]>; + +def HasV9_1aOps : SubtargetFeature<"v9.1a", "HasV9_1aOps", "true", + "Support ARM v9.1a instructions", + [HasV8_6aOps, HasV9_0aOps]>; + +def HasV9_2aOps : SubtargetFeature<"v9.2a", "HasV9_2aOps", "true", + "Support ARM v9.2a instructions", + [HasV8_7aOps, HasV9_1aOps]>; + def HasV8_1MMainlineOps : SubtargetFeature< "v8.1m.main", "HasV8_1MMainlineOps", "true", "Support ARM v8-1M Mainline instructions", @@ -867,6 +879,46 @@ FeatureRAS, FeatureDotProd]>; +def ARMv9a : Architecture<"armv9-a", "ARMv9a", [HasV9_0aOps, + FeatureAClass, + FeatureDB, + FeatureFPARMv8, + FeatureNEON, + FeatureDSP, + FeatureTrustZone, + FeatureMP, + FeatureVirtualization, + FeatureCrypto, + FeatureCRC, + FeatureRAS, + FeatureDotProd]>; +def ARMv91a : Architecture<"armv9.1-a", "ARMv91a", [HasV9_1aOps, + FeatureAClass, + FeatureDB, + FeatureFPARMv8, + FeatureNEON, + FeatureDSP, + FeatureTrustZone, + FeatureMP, + FeatureVirtualization, + FeatureCrypto, + FeatureCRC, + FeatureRAS, + FeatureDotProd]>; +def ARMv92a : Architecture<"armv9.2-a", "ARMv92a", [HasV9_2aOps, + FeatureAClass, + FeatureDB, + FeatureFPARMv8, + FeatureNEON, + FeatureDSP, + FeatureTrustZone, + FeatureMP, + FeatureVirtualization, + FeatureCrypto, + FeatureCRC, + FeatureRAS, + FeatureDotProd]>; + def ARMv8r : Architecture<"armv8-r", "ARMv8r", [HasV8Ops, FeatureRClass, FeatureDB, Index: llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp =================================================================== --- llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp +++ llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp @@ -3310,6 +3310,12 @@ Str += "ARMv8.6a"; else if (FBS[AArch64::HasV8_7aOps]) Str += "ARMv8.7a"; + else if (FBS[AArch64::HasV9_0aOps]) + Str += "ARMv9-a"; + else if (FBS[AArch64::HasV9_1aOps]) + Str += "ARMv9.1a"; + else if (FBS[AArch64::HasV9_2aOps]) + Str += "ARMv9.2a"; else { SmallVector<std::string, 2> ExtMatches; for (const auto& Ext : ExtensionMap) { @@ -5923,6 +5929,9 @@ case AArch64::ArchKind::ARMV8_5A: case AArch64::ArchKind::ARMV8_6A: case AArch64::ArchKind::ARMV8_7A: + case AArch64::ArchKind::ARMV9A: + case AArch64::ArchKind::ARMV9_1A: + case AArch64::ArchKind::ARMV9_2A: case AArch64::ArchKind::ARMV8R: RequestedExtensions.push_back("sm4"); RequestedExtensions.push_back("sha3"); @@ -5945,6 +5954,9 @@ case AArch64::ArchKind::ARMV8_5A: case AArch64::ArchKind::ARMV8_6A: case AArch64::ArchKind::ARMV8_7A: + case AArch64::ArchKind::ARMV9A: + case AArch64::ArchKind::ARMV9_1A: + case AArch64::ArchKind::ARMV9_2A: RequestedExtensions.push_back("nosm4"); RequestedExtensions.push_back("nosha3"); RequestedExtensions.push_back("nosha2"); Index: llvm/lib/Target/AArch64/AArch64Subtarget.h =================================================================== --- llvm/lib/Target/AArch64/AArch64Subtarget.h +++ llvm/lib/Target/AArch64/AArch64Subtarget.h @@ -89,6 +89,9 @@ bool HasV8_5aOps = false; bool HasV8_6aOps = false; bool HasV8_7aOps = false; + bool HasV9_0aOps = false; + bool HasV9_1aOps = false; + bool HasV9_2aOps = false; bool HasV8_0rOps = false; bool HasCONTEXTIDREL2 = false; @@ -343,6 +346,9 @@ bool hasV8_3aOps() const { return HasV8_3aOps; } bool hasV8_4aOps() const { return HasV8_4aOps; } bool hasV8_5aOps() const { return HasV8_5aOps; } + bool hasV9_0aOps() const { return HasV9_0aOps; } + bool hasV9_1aOps() const { return HasV9_1aOps; } + bool hasV9_2aOps() const { return HasV9_2aOps; } bool hasV8_0rOps() const { return HasV8_0rOps; } bool hasZeroCycleRegMove() const { return HasZeroCycleRegMove; } Index: llvm/lib/Target/AArch64/AArch64InstrInfo.td =================================================================== --- llvm/lib/Target/AArch64/AArch64InstrInfo.td +++ llvm/lib/Target/AArch64/AArch64InstrInfo.td @@ -27,6 +27,12 @@ AssemblerPredicate<(all_of HasV8_6aOps), "armv8.6a">; def HasV8_7a : Predicate<"Subtarget->hasV8_7aOps()">, AssemblerPredicate<(all_of HasV8_7aOps), "armv8.7a">; +def HasV9_0a : Predicate<"Subtarget->hasV9_0aOps()">, + AssemblerPredicate<(all_of HasV9_0aOps), "armv9-a">; +def HasV9_1a : Predicate<"Subtarget->hasV9_1aOps()">, + AssemblerPredicate<(all_of HasV9_1aOps), "armv9.1a">; +def HasV9_2a : Predicate<"Subtarget->hasV9_2aOps()">, + AssemblerPredicate<(all_of HasV9_2aOps), "armv9.2a">; def HasVH : Predicate<"Subtarget->hasVH()">, AssemblerPredicate<(all_of FeatureVH), "vh">; Index: llvm/lib/Target/AArch64/AArch64.td =================================================================== --- llvm/lib/Target/AArch64/AArch64.td +++ llvm/lib/Target/AArch64/AArch64.td @@ -476,6 +476,18 @@ "v8.7a", "HasV8_7aOps", "true", "Support ARM v8.7a instructions", [HasV8_6aOps, FeatureXS, FeatureWFxT, FeatureHCX]>; +def HasV9_0aOps : SubtargetFeature< + "v9a", "HasV9_0aOps", "true", "Support ARM v9a instructions", + [HasV8_5aOps, FeatureSVE2]>; + +def HasV9_1aOps : SubtargetFeature< + "v9.1a", "HasV9_1aOps", "true", "Support ARM v9.1a instructions", + [HasV8_6aOps, HasV9_0aOps]>; + +def HasV9_2aOps : SubtargetFeature< + "v9.2a", "HasV9_2aOps", "true", "Support ARM v9.2a instructions", + [HasV8_7aOps, HasV9_1aOps]>; + def HasV8_0rOps : SubtargetFeature< "v8r", "HasV8_0rOps", "true", "Support ARM v8r instructions", [//v8.1 Index: llvm/lib/Support/Triple.cpp =================================================================== --- llvm/lib/Support/Triple.cpp +++ llvm/lib/Support/Triple.cpp @@ -653,6 +653,12 @@ return Triple::ARMSubArch_v8_6a; case ARM::ArchKind::ARMV8_7A: return Triple::ARMSubArch_v8_7a; + case ARM::ArchKind::ARMV9A: + return Triple::ARMSubArch_v9; + case ARM::ArchKind::ARMV9_1A: + return Triple::ARMSubArch_v9_1a; + case ARM::ArchKind::ARMV9_2A: + return Triple::ARMSubArch_v9_2a; case ARM::ArchKind::ARMV8R: return Triple::ARMSubArch_v8r; case ARM::ArchKind::ARMV8MBaseline: Index: llvm/lib/Support/ARMTargetParser.cpp =================================================================== --- llvm/lib/Support/ARMTargetParser.cpp +++ llvm/lib/Support/ARMTargetParser.cpp @@ -82,6 +82,10 @@ case ArchKind::ARMV8MMainline: case ArchKind::ARMV8_1MMainline: return 8; + case ArchKind::ARMV9A: + case ArchKind::ARMV9_1A: + case ArchKind::ARMV9_2A: + return 9; case ArchKind::INVALID: return 0; } @@ -113,6 +117,9 @@ case ArchKind::ARMV8_5A: case ArchKind::ARMV8_6A: case ArchKind::ARMV8_7A: + case ArchKind::ARMV9A: + case ArchKind::ARMV9_1A: + case ArchKind::ARMV9_2A: return ProfileKind::A; case ArchKind::ARMV2: case ArchKind::ARMV2A: @@ -158,6 +165,9 @@ .Case("v8.6a", "v8.6-a") .Case("v8.7a", "v8.7-a") .Case("v8r", "v8-r") + .Cases("v9", "v9a", "v9-a") + .Case("v9.1a", "v9.1-a") + .Case("v9.2a", "v9.2-a") .Case("v8m.base", "v8-m.base") .Case("v8m.main", "v8-m.main") .Case("v8.1m.main", "v8.1-m.main") Index: llvm/lib/Support/AArch64TargetParser.cpp =================================================================== --- llvm/lib/Support/AArch64TargetParser.cpp +++ llvm/lib/Support/AArch64TargetParser.cpp @@ -98,6 +98,8 @@ Features.push_back("+sve2-sha3"); if (Extensions & AEK_SVE2BITPERM) Features.push_back("+sve2-bitperm"); + if (Extensions & AArch64::AEK_TME) + Features.push_back("+tme"); if (Extensions & AEK_RCPC) Features.push_back("+rcpc"); if (Extensions & AEK_BRBE) @@ -132,6 +134,12 @@ Features.push_back("+v8.6a"); if (AK == AArch64::ArchKind::ARMV8_7A) Features.push_back("+v8.7a"); + if (AK == AArch64::ArchKind::ARMV9A) + Features.push_back("+v9a"); + if (AK == AArch64::ArchKind::ARMV9_1A) + Features.push_back("+v9.1a"); + if (AK == AArch64::ArchKind::ARMV9_2A) + Features.push_back("+v9.2a"); if(AK == AArch64::ArchKind::ARMV8R) Features.push_back("+v8r"); Index: llvm/include/llvm/Support/ARMTargetParser.def =================================================================== --- llvm/include/llvm/Support/ARMTargetParser.def +++ llvm/include/llvm/Support/ARMTargetParser.def @@ -122,6 +122,21 @@ (ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP | ARM::AEK_CRC | ARM::AEK_RAS | ARM::AEK_DOTPROD | ARM::AEK_BF16 | ARM::AEK_I8MM)) +ARM_ARCH("armv9-a", ARMV9A, "9-A", "v9a", + ARMBuildAttrs::CPUArch::v8_A, FK_CRYPTO_NEON_FP_ARMV8, + (ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM | + ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP | ARM::AEK_CRC | ARM::AEK_RAS | + ARM::AEK_DOTPROD)) +ARM_ARCH("armv9.1-a", ARMV9_1A, "9.1-A", "v9.1a", + ARMBuildAttrs::CPUArch::v8_A, FK_CRYPTO_NEON_FP_ARMV8, + (ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM | + ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP | ARM::AEK_CRC | ARM::AEK_RAS | + ARM::AEK_DOTPROD | ARM::AEK_BF16 | ARM::AEK_I8MM)) +ARM_ARCH("armv9.2-a", ARMV9_2A, "9.2-A", "v9.2a", + ARMBuildAttrs::CPUArch::v8_A, FK_CRYPTO_NEON_FP_ARMV8, + (ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM | + ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP | ARM::AEK_CRC | ARM::AEK_RAS | + ARM::AEK_DOTPROD | ARM::AEK_BF16 | ARM::AEK_I8MM)) ARM_ARCH("armv8-r", ARMV8R, "8-R", "v8r", ARMBuildAttrs::CPUArch::v8_R, FK_NEON_FP_ARMV8, (ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB | Index: llvm/include/llvm/Support/AArch64TargetParser.def =================================================================== --- llvm/include/llvm/Support/AArch64TargetParser.def +++ llvm/include/llvm/Support/AArch64TargetParser.def @@ -58,6 +58,29 @@ AArch64::AEK_RDM | AArch64::AEK_RCPC | AArch64::AEK_DOTPROD | AArch64::AEK_SM4 | AArch64::AEK_SHA3 | AArch64::AEK_BF16 | AArch64::AEK_SHA2 | AArch64::AEK_AES | AArch64::AEK_I8MM)) +AARCH64_ARCH("armv9-a", ARMV9A, "9-A", "v9a", + ARMBuildAttrs::CPUArch::v8_A, FK_CRYPTO_NEON_FP_ARMV8, + (AArch64::AEK_CRC | AArch64::AEK_FP | + AArch64::AEK_SIMD | AArch64::AEK_RAS | AArch64::AEK_LSE | + AArch64::AEK_RDM | AArch64::AEK_RCPC | AArch64::AEK_DOTPROD | + AArch64::AEK_SM4 | AArch64::AEK_SHA3 | + AArch64::AEK_SHA2 | AArch64::AEK_AES | AArch64::AEK_SVE2)) +AARCH64_ARCH("armv9.1-a", ARMV9_1A, "9.1-A", "v9.1a", + ARMBuildAttrs::CPUArch::v8_A, FK_CRYPTO_NEON_FP_ARMV8, + (AArch64::AEK_CRC | AArch64::AEK_FP | + AArch64::AEK_SIMD | AArch64::AEK_RAS | AArch64::AEK_LSE | + AArch64::AEK_RDM | AArch64::AEK_RCPC | AArch64::AEK_DOTPROD | + AArch64::AEK_SM4 | AArch64::AEK_SHA3 | AArch64::AEK_BF16 | + AArch64::AEK_SHA2 | AArch64::AEK_AES | AArch64::AEK_I8MM | + AArch64::AEK_SVE2)) +AARCH64_ARCH("armv9.2-a", ARMV9_2A, "9.2-A", "v9.2a", + ARMBuildAttrs::CPUArch::v8_A, FK_CRYPTO_NEON_FP_ARMV8, + (AArch64::AEK_CRC | AArch64::AEK_FP | + AArch64::AEK_SIMD | AArch64::AEK_RAS | AArch64::AEK_LSE | + AArch64::AEK_RDM | AArch64::AEK_RCPC | AArch64::AEK_DOTPROD | + AArch64::AEK_SM4 | AArch64::AEK_SHA3 | AArch64::AEK_BF16 | + AArch64::AEK_SHA2 | AArch64::AEK_AES | AArch64::AEK_I8MM | + AArch64::AEK_SVE2)) // For v8-R, we do not enable crypto and align with GCC that enables a more // minimal set of optional architecture extensions. AARCH64_ARCH("armv8-r", ARMV8R, "8-R", "v8r", Index: llvm/include/llvm/ADT/Triple.h =================================================================== --- llvm/include/llvm/ADT/Triple.h +++ llvm/include/llvm/ADT/Triple.h @@ -106,6 +106,9 @@ enum SubArchType { NoSubArch, + ARMSubArch_v9_2a, + ARMSubArch_v9_1a, + ARMSubArch_v9, ARMSubArch_v8_7a, ARMSubArch_v8_6a, ARMSubArch_v8_5a, Index: clang/test/Preprocessor/arm-target-features.c =================================================================== --- clang/test/Preprocessor/arm-target-features.c +++ clang/test/Preprocessor/arm-target-features.c @@ -859,6 +859,21 @@ // CHECK-V87A: #define __ARM_ARCH_8_7A__ 1 // CHECK-V87A: #define __ARM_ARCH_PROFILE 'A' +// RUN: %clang -target armv9a-none-none-eabi -x c -E -dM %s -o - | FileCheck -match-full-lines --check-prefix=CHECK-V9A %s +// CHECK-V9A: #define __ARM_ARCH 9 +// CHECK-V9A: #define __ARM_ARCH_9A__ 1 +// CHECK-V9A: #define __ARM_ARCH_PROFILE 'A' + +// RUN: %clang -target armv9.1a-none-none-eabi -x c -E -dM %s -o - | FileCheck -match-full-lines --check-prefix=CHECK-V91A %s +// CHECK-V91A: #define __ARM_ARCH 9 +// CHECK-V91A: #define __ARM_ARCH_9_1A__ 1 +// CHECK-V91A: #define __ARM_ARCH_PROFILE 'A' + +// RUN: %clang -target armv9.2a-none-none-eabi -x c -E -dM %s -o - | FileCheck -match-full-lines --check-prefix=CHECK-V92A %s +// CHECK-V92A: #define __ARM_ARCH 9 +// CHECK-V92A: #define __ARM_ARCH_9_2A__ 1 +// CHECK-V92A: #define __ARM_ARCH_PROFILE 'A' + // RUN: %clang -target arm-none-none-eabi -march=armv7-m -mfpu=softvfp -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-SOFTVFP %s // CHECK-SOFTVFP-NOT: #define __ARM_FP 0x Index: clang/test/Preprocessor/aarch64-target-features.c =================================================================== --- clang/test/Preprocessor/aarch64-target-features.c +++ clang/test/Preprocessor/aarch64-target-features.c @@ -177,19 +177,16 @@ // CHECK-SVE-8_6-NOFEATURES-NOT: __ARM_FEATURE_SVE_MATMUL_INT8 1 // CHECK-SVE-8_6-NOFEATURES: __ARM_FEATURE_SVE 1 -// The following tests may need to be revised in the future since -// SVE2 is currently still part of Future Architecture Technologies -// (https://developer.arm.com/docs/ddi0602/latest) -// -// RUN: %clang -target aarch64-none-linux-gnu -march=armv8-a+sve2 -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-SVE2 %s +// RUN: %clang -target aarch64-none-linux-gnu -march=armv9-a -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-SVE2 %s +// RUN: %clang -target aarch64-none-linux-gnu -march=armv9-a+sve2 -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-SVE2 %s // CHECK-SVE2: __ARM_FEATURE_SVE2 1 -// RUN: %clang -target aarch64-none-linux-gnu -march=armv8-a+sve2-aes -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-SVE2AES %s +// RUN: %clang -target aarch64-none-linux-gnu -march=armv9-a+sve2-aes -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-SVE2AES %s // CHECK-SVE2AES: __ARM_FEATURE_SVE2_AES 1 -// RUN: %clang -target aarch64-none-linux-gnu -march=armv8-a+sve2-sha3 -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-SVE2SHA3 %s +// RUN: %clang -target aarch64-none-linux-gnu -march=armv9-a+sve2-sha3 -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-SVE2SHA3 %s // CHECK-SVE2SHA3: __ARM_FEATURE_SVE2_SHA3 1 -// RUN: %clang -target aarch64-none-linux-gnu -march=armv8-a+sve2-sm4 -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-SVE2SM4 %s +// RUN: %clang -target aarch64-none-linux-gnu -march=armv9-a+sve2-sm4 -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-SVE2SM4 %s // CHECK-SVE2SM4: __ARM_FEATURE_SVE2_SM4 1 -// RUN: %clang -target aarch64-none-linux-gnu -march=armv8-a+sve2-bitperm -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-SVE2BITPERM %s +// RUN: %clang -target aarch64-none-linux-gnu -march=armv9-a+sve2-bitperm -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-SVE2BITPERM %s // CHECK-SVE2BITPERM: __ARM_FEATURE_SVE2_BITPERM 1 // RUN: %clang -target aarch64-none-linux-gnu -march=armv8.2a+dotprod -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-DOTPROD %s Index: clang/test/Driver/arm-cortex-cpus.c =================================================================== --- clang/test/Driver/arm-cortex-cpus.c +++ clang/test/Driver/arm-cortex-cpus.c @@ -369,6 +369,57 @@ // RUN: %clang -target arm -march=armebv8.7-a -mbig-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-V87A %s // CHECK-BE-V87A: "-cc1"{{.*}} "-triple" "armebv8.7{{.*}}" "-target-cpu" "generic" +// RUN: %clang -target armv9a -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V9A %s +// RUN: %clang -target arm -march=armv9a -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V9A %s +// RUN: %clang -target arm -march=armv9-a -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V9A %s +// RUN: %clang -target arm -march=armv9a -mlittle-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V9A %s +// RUN: %clang -target armv9a -mlittle-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V9A %s +// RUN: %clang -target arm -march=armv9a -mlittle-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V9A %s +// RUN: %clang -target arm -mlittle-endian -march=armv9-a -mlittle-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V9A %s +// CHECK-V9A: "-cc1"{{.*}} "-triple" "armv9{{.*}}" "-target-cpu" "generic" + +// RUN: %clang -target armebv9a -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-V9A %s +// RUN: %clang -target armv9a -mbig-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-V9A %s +// RUN: %clang -target armeb -march=armebv9a -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-V9A %s +// RUN: %clang -target armeb -march=armebv9-a -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-V9A %s +// RUN: %clang -target arm -march=armebv9a -mbig-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-V9A %s +// RUN: %clang -target arm -march=armebv9-a -mbig-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-V9A %s +// CHECK-BE-V9A: "-cc1"{{.*}} "-triple" "armebv9{{.*}}" "-target-cpu" "generic" + +// RUN: %clang -target armv9.1a -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V91A %s +// RUN: %clang -target arm -march=armv9.1a -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V91A %s +// RUN: %clang -target arm -march=armv9.1-a -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V91A %s +// RUN: %clang -target arm -march=armv9.1a -mlittle-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V91A %s +// RUN: %clang -target armv9.1a -mlittle-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V91A %s +// RUN: %clang -target arm -march=armv9.1a -mlittle-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V91A %s +// RUN: %clang -target arm -mlittle-endian -march=armv9.1-a -mlittle-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V91A %s +// CHECK-V91A: "-cc1"{{.*}} "-triple" "armv9.1{{.*}}" "-target-cpu" "generic" + +// RUN: %clang -target armebv9.1a -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-V91A %s +// RUN: %clang -target armv9.1a -mbig-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-V91A %s +// RUN: %clang -target armeb -march=armebv9.1a -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-V91A %s +// RUN: %clang -target armeb -march=armebv9.1-a -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-V91A %s +// RUN: %clang -target arm -march=armebv9.1a -mbig-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-V91A %s +// RUN: %clang -target arm -march=armebv9.1-a -mbig-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-V91A %s +// CHECK-BE-V91A: "-cc1"{{.*}} "-triple" "armebv9.1{{.*}}" "-target-cpu" "generic" + +// RUN: %clang -target armv9.2a -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V92A %s +// RUN: %clang -target arm -march=armv9.2a -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V92A %s +// RUN: %clang -target arm -march=armv9.2-a -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V92A %s +// RUN: %clang -target arm -march=armv9.2a -mlittle-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V92A %s +// RUN: %clang -target armv9.2a -mlittle-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V92A %s +// RUN: %clang -target arm -march=armv9.2a -mlittle-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V92A %s +// RUN: %clang -target arm -mlittle-endian -march=armv9.2-a -mlittle-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V92A %s +// CHECK-V92A: "-cc1"{{.*}} "-triple" "armv9.2{{.*}}" "-target-cpu" "generic" + +// RUN: %clang -target armebv9.2a -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-V92A %s +// RUN: %clang -target armv9.2a -mbig-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-V92A %s +// RUN: %clang -target armeb -march=armebv9.2a -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-V92A %s +// RUN: %clang -target armeb -march=armebv9.2-a -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-V92A %s +// RUN: %clang -target arm -march=armebv9.2a -mbig-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-V92A %s +// RUN: %clang -target arm -march=armebv9.2-a -mbig-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-V92A %s +// CHECK-BE-V92A: "-cc1"{{.*}} "-triple" "armebv9.2{{.*}}" "-target-cpu" "generic" + // Once we have CPUs with optional v8.2-A FP16, we will need a way to turn it // on and off. Cortex-A53 is a placeholder for now. // RUN: %clang -target armv8a-linux-eabi -mcpu=cortex-a53+fp16 -### -c %s 2>&1 | FileCheck --check-prefix CHECK-CORTEX-A53-FP16 %s Index: clang/test/Driver/aarch64-cpus.c =================================================================== --- clang/test/Driver/aarch64-cpus.c +++ clang/test/Driver/aarch64-cpus.c @@ -768,6 +768,54 @@ // NO-LS64-NOT: "-target-feature" "+ls64" // LS64: "-target-feature" "+ls64" +// RUN: %clang -target aarch64 -march=armv9a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV9A %s +// RUN: %clang -target aarch64 -march=armv9-a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV9A %s +// RUN: %clang -target aarch64 -mlittle-endian -march=armv9a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV9A %s +// RUN: %clang -target aarch64 -mlittle-endian -march=armv9-a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV9A %s +// RUN: %clang -target aarch64_be -mlittle-endian -march=armv9a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV9A %s +// RUN: %clang -target aarch64_be -mlittle-endian -march=armv9-a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV9A %s +// GENERICV9A: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "generic" "-target-feature" "+neon" "-target-feature" "+v9a" + +// RUN: %clang -target aarch64_be -march=armv9a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV9A-BE %s +// RUN: %clang -target aarch64_be -march=armv9-a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV9A-BE %s +// RUN: %clang -target aarch64 -mbig-endian -march=armv9a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV9A-BE %s +// RUN: %clang -target aarch64 -mbig-endian -march=armv9-a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV9A-BE %s +// RUN: %clang -target aarch64_be -mbig-endian -march=armv9a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV9A-BE %s +// RUN: %clang -target aarch64_be -mbig-endian -march=armv9-a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV9A-BE %s +// GENERICV9A-BE: "-cc1"{{.*}} "-triple" "aarch64_be{{.*}}" "-target-cpu" "generic" "-target-feature" "+neon" "-target-feature" "+v9a" + +// RUN: %clang -target aarch64 -march=armv9.1a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV91A %s +// RUN: %clang -target aarch64 -march=armv9.1-a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV91A %s +// RUN: %clang -target aarch64 -mlittle-endian -march=armv9.1a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV91A %s +// RUN: %clang -target aarch64 -mlittle-endian -march=armv9.1-a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV91A %s +// RUN: %clang -target aarch64_be -mlittle-endian -march=armv9.1a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV91A %s +// RUN: %clang -target aarch64_be -mlittle-endian -march=armv9.1-a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV91A %s +// GENERICV91A: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "generic" "-target-feature" "+neon" "-target-feature" "+v9.1a" + +// RUN: %clang -target aarch64_be -march=armv9.1a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV91A-BE %s +// RUN: %clang -target aarch64_be -march=armv9.1-a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV91A-BE %s +// RUN: %clang -target aarch64 -mbig-endian -march=armv9.1a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV91A-BE %s +// RUN: %clang -target aarch64 -mbig-endian -march=armv9.1-a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV91A-BE %s +// RUN: %clang -target aarch64_be -mbig-endian -march=armv9.1a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV91A-BE %s +// RUN: %clang -target aarch64_be -mbig-endian -march=armv9.1-a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV91A-BE %s +// GENERICV91A-BE: "-cc1"{{.*}} "-triple" "aarch64_be{{.*}}" "-target-cpu" "generic" "-target-feature" "+neon" "-target-feature" "+v9.1a" + +// RUN: %clang -target aarch64 -march=armv9.2a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV92A %s +// RUN: %clang -target aarch64 -march=armv9.2-a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV92A %s +// RUN: %clang -target aarch64 -mlittle-endian -march=armv9.2a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV92A %s +// RUN: %clang -target aarch64 -mlittle-endian -march=armv9.2-a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV92A %s +// RUN: %clang -target aarch64_be -mlittle-endian -march=armv9.2a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV92A %s +// RUN: %clang -target aarch64_be -mlittle-endian -march=armv9.2-a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV92A %s +// GENERICV92A: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "generic" "-target-feature" "+neon" "-target-feature" "+v9.2a" + +// RUN: %clang -target aarch64_be -march=armv9.2a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV92A-BE %s +// RUN: %clang -target aarch64_be -march=armv9.2-a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV92A-BE %s +// RUN: %clang -target aarch64 -mbig-endian -march=armv9.2a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV92A-BE %s +// RUN: %clang -target aarch64 -mbig-endian -march=armv9.2-a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV92A-BE %s +// RUN: %clang -target aarch64_be -mbig-endian -march=armv9.2a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV92A-BE %s +// RUN: %clang -target aarch64_be -mbig-endian -march=armv9.2-a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV92A-BE %s +// GENERICV92A-BE: "-cc1"{{.*}} "-triple" "aarch64_be{{.*}}" "-target-cpu" "generic" "-target-feature" "+neon" "-target-feature" "+v9.2a" + // fullfp16 is off by default for v8a, feature must not be mentioned // RUN: %clang -target aarch64 -march=armv8a -### -c %s 2>&1 | FileCheck -check-prefix=V82ANOFP16 -check-prefix=GENERIC %s // RUN: %clang -target aarch64 -march=armv8-a -### -c %s 2>&1 | FileCheck -check-prefix=V82ANOFP16 -check-prefix=GENERIC %s Index: clang/lib/Driver/ToolChains/Arch/AArch64.cpp =================================================================== --- clang/lib/Driver/ToolChains/Arch/AArch64.cpp +++ clang/lib/Driver/ToolChains/Arch/AArch64.cpp @@ -79,10 +79,13 @@ else return false; - // +sve implies +f32mm if the base architecture is v8.6A or v8.7A - // it isn't the case in general that sve implies both f64mm and f32mm + // +sve implies +f32mm if the base architecture is v8.6A, v8.7A, v9.1A or + // v9.2A. It isn't the case in general that sve implies both f64mm and f32mm if ((ArchKind == llvm::AArch64::ArchKind::ARMV8_6A || - ArchKind == llvm::AArch64::ArchKind::ARMV8_7A) && Feature == "sve") + ArchKind == llvm::AArch64::ArchKind::ARMV8_7A || + ArchKind == llvm::AArch64::ArchKind::ARMV9_1A || + ArchKind == llvm::AArch64::ArchKind::ARMV9_2A) && + Feature == "sve") Features.push_back("+f32mm"); } return true; @@ -345,7 +348,10 @@ NoCrypto = true; } - if (std::find(ItBegin, ItEnd, "+v8.4a") != ItEnd) { + if (std::find(ItBegin, ItEnd, "+v8.4a") != ItEnd || + std::find(ItBegin, ItEnd, "+v9a") != ItEnd || + std::find(ItBegin, ItEnd, "+v9.1a") != ItEnd || + std::find(ItBegin, ItEnd, "+v9.2a") != ItEnd) { if (HasCrypto && !NoCrypto) { // Check if we have NOT disabled an algorithm with something like: // +crypto, -algorithm @@ -404,9 +410,18 @@ } } - auto V8_6Pos = llvm::find(Features, "+v8.6a"); - if (V8_6Pos != std::end(Features)) - V8_6Pos = Features.insert(std::next(V8_6Pos), {"+i8mm", "+bf16"}); + const char *Archs[] = {"+v8.6a", "+v8.7a", "+v9.1a", "+v9.2a"}; + auto Pos = std::find_first_of(Features.begin(), Features.end(), + std::begin(Archs), std::end(Archs)); + if (Pos != std::end(Features)) + Pos = Features.insert(std::next(Pos), {"+i8mm", "+bf16"}); + + // Enable SVE2 by default on Armv9-A + const char *SVE2Archs[] = {"+v9a", "+v9.1a", "+v9.2a"}; + Pos = std::find_first_of(Features.begin(), Features.end(), + std::begin(SVE2Archs), std::end(SVE2Archs)); + if (Pos != Features.end()) + Features.push_back("+sve2"); if (Arg *A = Args.getLastArg(options::OPT_mno_unaligned_access, options::OPT_munaligned_access)) { Index: clang/lib/Basic/Targets/ARM.cpp =================================================================== --- clang/lib/Basic/Targets/ARM.cpp +++ clang/lib/Basic/Targets/ARM.cpp @@ -212,6 +212,12 @@ return "8_6A"; case llvm::ARM::ArchKind::ARMV8_7A: return "8_7A"; + case llvm::ARM::ArchKind::ARMV9A: + return "9A"; + case llvm::ARM::ArchKind::ARMV9_1A: + return "9_1A"; + case llvm::ARM::ArchKind::ARMV9_2A: + return "9_2A"; case llvm::ARM::ArchKind::ARMV8MBaseline: return "8M_BASE"; case llvm::ARM::ArchKind::ARMV8MMainline: @@ -535,6 +541,7 @@ LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B; break; case 8: + case 9: LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B; } @@ -877,6 +884,9 @@ case llvm::ARM::ArchKind::ARMV8_4A: case llvm::ARM::ArchKind::ARMV8_5A: case llvm::ARM::ArchKind::ARMV8_6A: + case llvm::ARM::ArchKind::ARMV9A: + case llvm::ARM::ArchKind::ARMV9_1A: + case llvm::ARM::ArchKind::ARMV9_2A: getTargetDefinesARMV83A(Opts, Builder); break; } Index: clang/lib/Basic/Targets/AArch64.h =================================================================== --- clang/lib/Basic/Targets/AArch64.h +++ clang/lib/Basic/Targets/AArch64.h @@ -91,6 +91,12 @@ MacroBuilder &Builder) const; void getTargetDefinesARMV87A(const LangOptions &Opts, MacroBuilder &Builder) const; + void getTargetDefinesARMV9A(const LangOptions &Opts, + MacroBuilder &Builder) const; + void getTargetDefinesARMV91A(const LangOptions &Opts, + MacroBuilder &Builder) const; + void getTargetDefinesARMV92A(const LangOptions &Opts, + MacroBuilder &Builder) const; void getTargetDefines(const LangOptions &Opts, MacroBuilder &Builder) const override; Index: clang/lib/Basic/Targets/AArch64.cpp =================================================================== --- clang/lib/Basic/Targets/AArch64.cpp +++ clang/lib/Basic/Targets/AArch64.cpp @@ -40,6 +40,17 @@ #include "clang/Basic/BuiltinsAArch64.def" }; +static StringRef getArchVersionString(llvm::AArch64::ArchKind Kind) { + switch (Kind) { + case llvm::AArch64::ArchKind::ARMV9A: + case llvm::AArch64::ArchKind::ARMV9_1A: + case llvm::AArch64::ArchKind::ARMV9_2A: + return "9"; + default: + return "8"; + } +} + AArch64TargetInfo::AArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) : TargetInfo(Triple), ABI("aapcs") { @@ -203,6 +214,24 @@ getTargetDefinesARMV86A(Opts, Builder); } +void AArch64TargetInfo::getTargetDefinesARMV9A(const LangOptions &Opts, + MacroBuilder &Builder) const { + // Armv9-A maps to Armv8.5-A + getTargetDefinesARMV85A(Opts, Builder); +} + +void AArch64TargetInfo::getTargetDefinesARMV91A(const LangOptions &Opts, + MacroBuilder &Builder) const { + // Armv9.1-A maps to Armv8.6-A + getTargetDefinesARMV86A(Opts, Builder); +} + +void AArch64TargetInfo::getTargetDefinesARMV92A(const LangOptions &Opts, + MacroBuilder &Builder) const { + // Armv9.2-A maps to Armv8.7-A + getTargetDefinesARMV87A(Opts, Builder); +} + void AArch64TargetInfo::getTargetDefines(const LangOptions &Opts, MacroBuilder &Builder) const { // Target identification. @@ -227,7 +256,7 @@ // ACLE predefines. Many can only have one possible value on v8 AArch64. Builder.defineMacro("__ARM_ACLE", "200"); - Builder.defineMacro("__ARM_ARCH", "8"); + Builder.defineMacro("__ARM_ARCH", getArchVersionString(ArchKind)); Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'"); Builder.defineMacro("__ARM_64BIT_STATE", "1"); @@ -405,6 +434,15 @@ case llvm::AArch64::ArchKind::ARMV8_7A: getTargetDefinesARMV87A(Opts, Builder); break; + case llvm::AArch64::ArchKind::ARMV9A: + getTargetDefinesARMV9A(Opts, Builder); + break; + case llvm::AArch64::ArchKind::ARMV9_1A: + getTargetDefinesARMV91A(Opts, Builder); + break; + case llvm::AArch64::ArchKind::ARMV9_2A: + getTargetDefinesARMV92A(Opts, Builder); + break; } // All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8) builtins work. @@ -550,6 +588,12 @@ ArchKind = llvm::AArch64::ArchKind::ARMV8_6A; if (Feature == "+v8.7a") ArchKind = llvm::AArch64::ArchKind::ARMV8_7A; + if (Feature == "+v9a") + ArchKind = llvm::AArch64::ArchKind::ARMV9A; + if (Feature == "+v9.1a") + ArchKind = llvm::AArch64::ArchKind::ARMV9_1A; + if (Feature == "+v9.2a") + ArchKind = llvm::AArch64::ArchKind::ARMV9_2A; if (Feature == "+v8r") ArchKind = llvm::AArch64::ArchKind::ARMV8R; if (Feature == "+fullfp16")
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