Conanap created this revision.
Conanap added reviewers: PowerPC, nemanjai, saghir.
Conanap added projects: PowerPC, LLVM, clang.
Herald added subscribers: kbarton, hiraditya.
Conanap requested review of this revision.
This patch removes the uneccessary mf/mtvsr generated in conjunction
with xscvdpsxws/xscvdpuxws.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D109902
Files:
llvm/lib/Target/PowerPC/PPCInstrVSX.td
llvm/test/CodeGen/PowerPC/build-vector-tests.ll
llvm/test/CodeGen/PowerPC/test-vector-insert.ll
llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i32_elts.ll
Index: llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i32_elts.ll
===================================================================
--- llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i32_elts.ll
+++ llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i32_elts.ll
@@ -13,12 +13,8 @@
; CHECK-P8-LABEL: test2elt:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: xxswapd vs0, v2
-; CHECK-P8-NEXT: xscvdpuxws f1, v2
-; CHECK-P8-NEXT: xscvdpuxws f0, f0
-; CHECK-P8-NEXT: mffprwz r3, f1
-; CHECK-P8-NEXT: mtvsrwz v2, r3
-; CHECK-P8-NEXT: mffprwz r4, f0
-; CHECK-P8-NEXT: mtvsrwz v3, r4
+; CHECK-P8-NEXT: xscvdpsxws v2, v2
+; CHECK-P8-NEXT: xscvdpsxws v3, f0
; CHECK-P8-NEXT: vmrghw v2, v2, v3
; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: mffprd r3, f0
@@ -26,26 +22,18 @@
;
; CHECK-P9-LABEL: test2elt:
; CHECK-P9: # %bb.0: # %entry
-; CHECK-P9-NEXT: xscvdpuxws f0, v2
-; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: xxswapd vs0, v2
-; CHECK-P9-NEXT: mtvsrwz v3, r3
-; CHECK-P9-NEXT: xscvdpuxws f0, f0
-; CHECK-P9-NEXT: mffprwz r3, f0
-; CHECK-P9-NEXT: mtvsrwz v2, r3
+; CHECK-P9-NEXT: xscvdpsxws v3, v2
+; CHECK-P9-NEXT: xscvdpsxws v2, f0
; CHECK-P9-NEXT: vmrghw v2, v3, v2
; CHECK-P9-NEXT: mfvsrld r3, v2
; CHECK-P9-NEXT: blr
;
; CHECK-BE-LABEL: test2elt:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: xscvdpuxws f0, v2
-; CHECK-BE-NEXT: mffprwz r3, f0
; CHECK-BE-NEXT: xxswapd vs0, v2
-; CHECK-BE-NEXT: mtvsrwz v3, r3
-; CHECK-BE-NEXT: xscvdpuxws f0, f0
-; CHECK-BE-NEXT: mffprwz r3, f0
-; CHECK-BE-NEXT: mtvsrwz v2, r3
+; CHECK-BE-NEXT: xscvdpsxws v3, v2
+; CHECK-BE-NEXT: xscvdpsxws v2, f0
; CHECK-BE-NEXT: vmrgow v2, v3, v2
; CHECK-BE-NEXT: mfvsrd r3, v2
; CHECK-BE-NEXT: blr
@@ -305,12 +293,8 @@
; CHECK-P8-LABEL: test2elt_signed:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: xxswapd vs0, v2
-; CHECK-P8-NEXT: xscvdpsxws f1, v2
-; CHECK-P8-NEXT: xscvdpsxws f0, f0
-; CHECK-P8-NEXT: mffprwz r3, f1
-; CHECK-P8-NEXT: mtvsrwz v2, r3
-; CHECK-P8-NEXT: mffprwz r4, f0
-; CHECK-P8-NEXT: mtvsrwz v3, r4
+; CHECK-P8-NEXT: xscvdpsxws v2, v2
+; CHECK-P8-NEXT: xscvdpsxws v3, f0
; CHECK-P8-NEXT: vmrghw v2, v2, v3
; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: mffprd r3, f0
@@ -318,26 +302,18 @@
;
; CHECK-P9-LABEL: test2elt_signed:
; CHECK-P9: # %bb.0: # %entry
-; CHECK-P9-NEXT: xscvdpsxws f0, v2
-; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: xxswapd vs0, v2
-; CHECK-P9-NEXT: mtvsrwz v3, r3
-; CHECK-P9-NEXT: xscvdpsxws f0, f0
-; CHECK-P9-NEXT: mffprwz r3, f0
-; CHECK-P9-NEXT: mtvsrwz v2, r3
+; CHECK-P9-NEXT: xscvdpsxws v3, v2
+; CHECK-P9-NEXT: xscvdpsxws v2, f0
; CHECK-P9-NEXT: vmrghw v2, v3, v2
; CHECK-P9-NEXT: mfvsrld r3, v2
; CHECK-P9-NEXT: blr
;
; CHECK-BE-LABEL: test2elt_signed:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: xscvdpsxws f0, v2
-; CHECK-BE-NEXT: mffprwz r3, f0
; CHECK-BE-NEXT: xxswapd vs0, v2
-; CHECK-BE-NEXT: mtvsrwz v3, r3
-; CHECK-BE-NEXT: xscvdpsxws f0, f0
-; CHECK-BE-NEXT: mffprwz r3, f0
-; CHECK-BE-NEXT: mtvsrwz v2, r3
+; CHECK-BE-NEXT: xscvdpsxws v3, v2
+; CHECK-BE-NEXT: xscvdpsxws v2, f0
; CHECK-BE-NEXT: vmrgow v2, v3, v2
; CHECK-BE-NEXT: mfvsrd r3, v2
; CHECK-BE-NEXT: blr
Index: llvm/test/CodeGen/PowerPC/test-vector-insert.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/test-vector-insert.ll
@@ -0,0 +1,172 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; xscvdpsxws and uxws is only available on Power7 and above
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN: < %s | FileCheck %s --check-prefix=CHECK-LE
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN: -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-BE
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN: -mcpu=pwr7 < %s | FileCheck %s
+
+define dso_local <4 x i32> @test(<4 x i32> %a, double %b) {
+; CHECK-LE-LABEL: test:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: xscvdpsxws 35, 1
+; CHECK-LE-NEXT: addis 3, 2, .LCPI0_0@toc@ha
+; CHECK-LE-NEXT: addi 3, 3, .LCPI0_0@toc@l
+; CHECK-LE-NEXT: lvx 4, 0, 3
+; CHECK-LE-NEXT: vperm 2, 3, 2, 4
+; CHECK-LE-NEXT: blr
+;
+; CHECK-BE-LABEL: test:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: xscvdpsxws 0, 1
+; CHECK-BE-NEXT: addi 3, 1, -4
+; CHECK-BE-NEXT: stfiwx 0, 0, 3
+; CHECK-BE-NEXT: lwz 3, -4(1)
+; CHECK-BE-NEXT: xxsldwi 0, 34, 34, 3
+; CHECK-BE-NEXT: stw 3, -32(1)
+; CHECK-BE-NEXT: addi 3, 1, -32
+; CHECK-BE-NEXT: lxvw4x 1, 0, 3
+; CHECK-BE-NEXT: xxsldwi 34, 0, 1, 1
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LABEL: test:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xscvdpsxws 0, 1
+; CHECK-NEXT: addi 3, 1, -4
+; CHECK-NEXT: stfiwx 0, 0, 3
+; CHECK-NEXT: lwz 3, -4(1)
+; CHECK-NEXT: xxsldwi 0, 34, 34, 3
+; CHECK-NEXT: stw 3, -32(1)
+; CHECK-NEXT: addi 3, 1, -32
+; CHECK-NEXT: lxvw4x 1, 0, 3
+; CHECK-NEXT: xxsldwi 34, 0, 1, 1
+; CHECK-NEXT: blr
+entry:
+ %conv = fptosi double %b to i32
+ %vecins = insertelement <4 x i32> %a, i32 %conv, i32 3
+ ret <4 x i32> %vecins
+}
+
+define dso_local <4 x i32> @test2(<4 x i32> %a, float %b) {
+; CHECK-LE-LABEL: test2:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: xscvdpsxws 35, 1
+; CHECK-LE-NEXT: addis 3, 2, .LCPI1_0@toc@ha
+; CHECK-LE-NEXT: addi 3, 3, .LCPI1_0@toc@l
+; CHECK-LE-NEXT: lvx 4, 0, 3
+; CHECK-LE-NEXT: vperm 2, 3, 2, 4
+; CHECK-LE-NEXT: blr
+;
+; CHECK-BE-LABEL: test2:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: xscvdpsxws 0, 1
+; CHECK-BE-NEXT: addi 3, 1, -4
+; CHECK-BE-NEXT: stfiwx 0, 0, 3
+; CHECK-BE-NEXT: lwz 3, -4(1)
+; CHECK-BE-NEXT: xxsldwi 0, 34, 34, 3
+; CHECK-BE-NEXT: stw 3, -32(1)
+; CHECK-BE-NEXT: addi 3, 1, -32
+; CHECK-BE-NEXT: lxvw4x 1, 0, 3
+; CHECK-BE-NEXT: xxsldwi 34, 0, 1, 1
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LABEL: test2:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xscvdpsxws 0, 1
+; CHECK-NEXT: addi 3, 1, -4
+; CHECK-NEXT: stfiwx 0, 0, 3
+; CHECK-NEXT: lwz 3, -4(1)
+; CHECK-NEXT: xxsldwi 0, 34, 34, 3
+; CHECK-NEXT: stw 3, -32(1)
+; CHECK-NEXT: addi 3, 1, -32
+; CHECK-NEXT: lxvw4x 1, 0, 3
+; CHECK-NEXT: xxsldwi 34, 0, 1, 1
+; CHECK-NEXT: blr
+entry:
+ %conv = fptosi float %b to i32
+ %vecins = insertelement <4 x i32> %a, i32 %conv, i32 3
+ ret <4 x i32> %vecins
+}
+
+define dso_local <4 x i32> @test3(<4 x i32> %a, double %b) {
+; CHECK-LE-LABEL: test3:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: xscvdpsxws 35, 1
+; CHECK-LE-NEXT: addis 3, 2, .LCPI2_0@toc@ha
+; CHECK-LE-NEXT: addi 3, 3, .LCPI2_0@toc@l
+; CHECK-LE-NEXT: lvx 4, 0, 3
+; CHECK-LE-NEXT: vperm 2, 3, 2, 4
+; CHECK-LE-NEXT: blr
+;
+; CHECK-BE-LABEL: test3:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: xscvdpuxws 0, 1
+; CHECK-BE-NEXT: addi 3, 1, -4
+; CHECK-BE-NEXT: stfiwx 0, 0, 3
+; CHECK-BE-NEXT: lwz 3, -4(1)
+; CHECK-BE-NEXT: xxsldwi 0, 34, 34, 3
+; CHECK-BE-NEXT: stw 3, -32(1)
+; CHECK-BE-NEXT: addi 3, 1, -32
+; CHECK-BE-NEXT: lxvw4x 1, 0, 3
+; CHECK-BE-NEXT: xxsldwi 34, 0, 1, 1
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LABEL: test3:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xscvdpuxws 0, 1
+; CHECK-NEXT: addi 3, 1, -4
+; CHECK-NEXT: stfiwx 0, 0, 3
+; CHECK-NEXT: lwz 3, -4(1)
+; CHECK-NEXT: xxsldwi 0, 34, 34, 3
+; CHECK-NEXT: stw 3, -32(1)
+; CHECK-NEXT: addi 3, 1, -32
+; CHECK-NEXT: lxvw4x 1, 0, 3
+; CHECK-NEXT: xxsldwi 34, 0, 1, 1
+; CHECK-NEXT: blr
+entry:
+ %conv = fptoui double %b to i32
+ %vecins = insertelement <4 x i32> %a, i32 %conv, i32 3
+ ret <4 x i32> %vecins
+}
+
+define dso_local <4 x i32> @test4(<4 x i32> %a, float %b) {
+; CHECK-LE-LABEL: test4:
+; CHECK-LE: # %bb.0: # %entry
+; CHECK-LE-NEXT: xscvdpsxws 35, 1
+; CHECK-LE-NEXT: addis 3, 2, .LCPI3_0@toc@ha
+; CHECK-LE-NEXT: addi 3, 3, .LCPI3_0@toc@l
+; CHECK-LE-NEXT: lvx 4, 0, 3
+; CHECK-LE-NEXT: vperm 2, 3, 2, 4
+; CHECK-LE-NEXT: blr
+;
+; CHECK-BE-LABEL: test4:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT: xscvdpuxws 0, 1
+; CHECK-BE-NEXT: addi 3, 1, -4
+; CHECK-BE-NEXT: stfiwx 0, 0, 3
+; CHECK-BE-NEXT: lwz 3, -4(1)
+; CHECK-BE-NEXT: xxsldwi 0, 34, 34, 3
+; CHECK-BE-NEXT: stw 3, -32(1)
+; CHECK-BE-NEXT: addi 3, 1, -32
+; CHECK-BE-NEXT: lxvw4x 1, 0, 3
+; CHECK-BE-NEXT: xxsldwi 34, 0, 1, 1
+; CHECK-BE-NEXT: blr
+;
+; CHECK-LABEL: test4:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xscvdpuxws 0, 1
+; CHECK-NEXT: addi 3, 1, -4
+; CHECK-NEXT: stfiwx 0, 0, 3
+; CHECK-NEXT: lwz 3, -4(1)
+; CHECK-NEXT: xxsldwi 0, 34, 34, 3
+; CHECK-NEXT: stw 3, -32(1)
+; CHECK-NEXT: addi 3, 1, -32
+; CHECK-NEXT: lxvw4x 1, 0, 3
+; CHECK-NEXT: xxsldwi 34, 0, 1, 1
+; CHECK-NEXT: blr
+entry:
+ %conv = fptoui float %b to i32
+ %vecins = insertelement <4 x i32> %a, i32 %conv, i32 3
+ ret <4 x i32> %vecins
+}
Index: llvm/test/CodeGen/PowerPC/build-vector-tests.ll
===================================================================
--- llvm/test/CodeGen/PowerPC/build-vector-tests.ll
+++ llvm/test/CodeGen/PowerPC/build-vector-tests.ll
@@ -1711,28 +1711,28 @@
define <4 x i32> @spltMemValConvftoi(float* nocapture readonly %ptr) {
; P9BE-LABEL: spltMemValConvftoi:
; P9BE: # %bb.0: # %entry
-; P9BE-NEXT: lfiwzx f0, 0, r3
-; P9BE-NEXT: xvcvspsxws vs0, vs0
+; P9BE-NEXT: lfs f0, 0(r3)
+; P9BE-NEXT: xscvdpsxws f0, f0
; P9BE-NEXT: xxspltw v2, vs0, 1
; P9BE-NEXT: blr
;
; P9LE-LABEL: spltMemValConvftoi:
; P9LE: # %bb.0: # %entry
-; P9LE-NEXT: lfiwzx f0, 0, r3
-; P9LE-NEXT: xvcvspsxws vs0, vs0
+; P9LE-NEXT: lfs f0, 0(r3)
+; P9LE-NEXT: xscvdpsxws f0, f0
; P9LE-NEXT: xxspltw v2, vs0, 1
; P9LE-NEXT: blr
;
; P8BE-LABEL: spltMemValConvftoi:
; P8BE: # %bb.0: # %entry
-; P8BE-NEXT: lfsx f0, 0, r3
+; P8BE-NEXT: lfs f0, 0(r3)
; P8BE-NEXT: xscvdpsxws f0, f0
; P8BE-NEXT: xxspltw v2, vs0, 1
; P8BE-NEXT: blr
;
; P8LE-LABEL: spltMemValConvftoi:
; P8LE: # %bb.0: # %entry
-; P8LE-NEXT: lfsx f0, 0, r3
+; P8LE-NEXT: lfs f0, 0(r3)
; P8LE-NEXT: xscvdpsxws f0, f0
; P8LE-NEXT: xxspltw v2, vs0, 1
; P8LE-NEXT: blr
@@ -2209,14 +2209,14 @@
;
; P8BE-LABEL: spltMemValConvdtoi:
; P8BE: # %bb.0: # %entry
-; P8BE-NEXT: lfdx f0, 0, r3
+; P8BE-NEXT: lfd f0, 0(r3)
; P8BE-NEXT: xscvdpsxws f0, f0
; P8BE-NEXT: xxspltw v2, vs0, 1
; P8BE-NEXT: blr
;
; P8LE-LABEL: spltMemValConvdtoi:
; P8LE: # %bb.0: # %entry
-; P8LE-NEXT: lfdx f0, 0, r3
+; P8LE-NEXT: lfd f0, 0(r3)
; P8LE-NEXT: xscvdpsxws f0, f0
; P8LE-NEXT: xxspltw v2, vs0, 1
; P8LE-NEXT: blr
@@ -3231,29 +3231,29 @@
define <4 x i32> @spltMemValConvftoui(float* nocapture readonly %ptr) {
; P9BE-LABEL: spltMemValConvftoui:
; P9BE: # %bb.0: # %entry
-; P9BE-NEXT: lfiwzx f0, 0, r3
-; P9BE-NEXT: xvcvspuxws vs0, vs0
+; P9BE-NEXT: lfs f0, 0(r3)
+; P9BE-NEXT: xscvdpsxws f0, f0
; P9BE-NEXT: xxspltw v2, vs0, 1
; P9BE-NEXT: blr
;
; P9LE-LABEL: spltMemValConvftoui:
; P9LE: # %bb.0: # %entry
-; P9LE-NEXT: lfiwzx f0, 0, r3
-; P9LE-NEXT: xvcvspuxws vs0, vs0
+; P9LE-NEXT: lfs f0, 0(r3)
+; P9LE-NEXT: xscvdpsxws f0, f0
; P9LE-NEXT: xxspltw v2, vs0, 1
; P9LE-NEXT: blr
;
; P8BE-LABEL: spltMemValConvftoui:
; P8BE: # %bb.0: # %entry
-; P8BE-NEXT: lfsx f0, 0, r3
-; P8BE-NEXT: xscvdpuxws f0, f0
+; P8BE-NEXT: lfs f0, 0(r3)
+; P8BE-NEXT: xscvdpsxws f0, f0
; P8BE-NEXT: xxspltw v2, vs0, 1
; P8BE-NEXT: blr
;
; P8LE-LABEL: spltMemValConvftoui:
; P8LE: # %bb.0: # %entry
-; P8LE-NEXT: lfsx f0, 0, r3
-; P8LE-NEXT: xscvdpuxws f0, f0
+; P8LE-NEXT: lfs f0, 0(r3)
+; P8LE-NEXT: xscvdpsxws f0, f0
; P8LE-NEXT: xxspltw v2, vs0, 1
; P8LE-NEXT: blr
entry:
@@ -3716,28 +3716,28 @@
; P9BE-LABEL: spltMemValConvdtoui:
; P9BE: # %bb.0: # %entry
; P9BE-NEXT: lfd f0, 0(r3)
-; P9BE-NEXT: xscvdpuxws f0, f0
+; P9BE-NEXT: xscvdpsxws f0, f0
; P9BE-NEXT: xxspltw v2, vs0, 1
; P9BE-NEXT: blr
;
; P9LE-LABEL: spltMemValConvdtoui:
; P9LE: # %bb.0: # %entry
; P9LE-NEXT: lfd f0, 0(r3)
-; P9LE-NEXT: xscvdpuxws f0, f0
+; P9LE-NEXT: xscvdpsxws f0, f0
; P9LE-NEXT: xxspltw v2, vs0, 1
; P9LE-NEXT: blr
;
; P8BE-LABEL: spltMemValConvdtoui:
; P8BE: # %bb.0: # %entry
-; P8BE-NEXT: lfdx f0, 0, r3
-; P8BE-NEXT: xscvdpuxws f0, f0
+; P8BE-NEXT: lfd f0, 0(r3)
+; P8BE-NEXT: xscvdpsxws f0, f0
; P8BE-NEXT: xxspltw v2, vs0, 1
; P8BE-NEXT: blr
;
; P8LE-LABEL: spltMemValConvdtoui:
; P8LE: # %bb.0: # %entry
-; P8LE-NEXT: lfdx f0, 0, r3
-; P8LE-NEXT: xscvdpuxws f0, f0
+; P8LE-NEXT: lfd f0, 0(r3)
+; P8LE-NEXT: xscvdpsxws f0, f0
; P8LE-NEXT: xxspltw v2, vs0, 1
; P8LE-NEXT: blr
entry:
Index: llvm/lib/Target/PowerPC/PPCInstrVSX.td
===================================================================
--- llvm/lib/Target/PowerPC/PPCInstrVSX.td
+++ llvm/lib/Target/PowerPC/PPCInstrVSX.td
@@ -2492,6 +2492,13 @@
v16i8:$b, v16i8:$c)),
(v16i8 (VPERMXOR $a, $b, $c))>;
+let AddedComplexity = 700 in {
+def : Pat<(v4i32 (PPCSToV DblToInt.A)),
+ (v4i32 (SUBREG_TO_REG (i64 1), (XSCVDPSXWS f64:$A), sub_64))>;
+def : Pat<(v4i32 (PPCSToV DblToUInt.A)),
+ (v4i32 (SUBREG_TO_REG (i64 1), (XSCVDPSXWS f64:$A), sub_64))>;
+}
+
let AddedComplexity = 400 in {
// Valid for any VSX subtarget, regardless of endianness.
let Predicates = [HasVSX] in {
@@ -2800,6 +2807,7 @@
def : Pat<(v4i32 (build_vector DblToInt.A, DblToInt.A,
DblToInt.A, DblToInt.A)),
(v4i32 (XXSPLTW (SUBREG_TO_REG (i64 1), (XSCVDPSXWS $A), sub_64), 1))>;
+
def : Pat<(v4i32 (build_vector DblToUInt.A, DblToUInt.A,
DblToUInt.A, DblToUInt.A)),
(v4i32 (XXSPLTW (SUBREG_TO_REG (i64 1), (XSCVDPUXWS $A), sub_64), 1))>;
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