craig.topper added inline comments. ================ Comment at: lib/CodeGen/CGBuiltin.cpp:6304 @@ +6303,3 @@ + Indices[i] = i; + Ops[2] = CGF.Builder.CreateShuffleVector(Ops[2], Ops[2], + makeArrayRef(Indices, NumElts), ---------------- delena wrote: > What code do you receive at the end? There is no shuffle instruction in the > architecture for mask vector. That's not really a shuffle. It's an extract subvector, but the IR doesn't have a real instruction for that.
It's needed so we can go from i8 -> v8i1 -> v2i1/v4i1. ================ Comment at: test/CodeGen/avx512f-builtins.c:123 @@ -122,2 +122,3 @@ // CHECK-LABEL: @test_mm512_storeu_si512 - // CHECK: @llvm.x86.avx512.mask.storeu.d.512 + // CHECK: store <16 x i32> %5, <16 x i32>* %6, align 1 + // CHECK-NEXT: ret void ---------------- delena wrote: > I suggest to remove %5, %6 from the test, you can put something like this: > CHECK: store <16 x i32> {{.*}}, align 1 I'll clean that up. I fixed most of them but looks like a missed a few. http://reviews.llvm.org/D20782 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits