Author: Craig Topper Date: 2021-10-14T09:25:03-07:00 New Revision: f7ba572483dd424c6235901d1c6cb3650c46b477
URL: https://github.com/llvm/llvm-project/commit/f7ba572483dd424c6235901d1c6cb3650c46b477 DIFF: https://github.com/llvm/llvm-project/commit/f7ba572483dd424c6235901d1c6cb3650c46b477.diff LOG: [RISCV] Update Zba, Zbb, Zbc, and Zbs version from 0.93 to 1.0. I've removed the Zbs W instructions that are not part of the frozen spec. References to B as an extension name have been removed. Tests are updated or split accordingly. Reviewed By: luismarques Differential Revision: https://reviews.llvm.org/D110669 Added: Modified: clang/lib/Basic/Targets/RISCV.cpp clang/lib/Driver/ToolChains/Arch/RISCV.cpp clang/test/Driver/riscv-arch.c clang/test/Preprocessor/riscv-target-features.c llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp llvm/lib/Target/RISCV/RISCVInstrInfoZb.td llvm/test/CodeGen/RISCV/attributes.ll llvm/test/MC/RISCV/attribute-arch.s Removed: ################################################################################ diff --git a/clang/lib/Basic/Targets/RISCV.cpp b/clang/lib/Basic/Targets/RISCV.cpp index fa56cddca2a2f..00da8cdaef0b5 100644 --- a/clang/lib/Basic/Targets/RISCV.cpp +++ b/clang/lib/Basic/Targets/RISCV.cpp @@ -182,13 +182,13 @@ void RISCVTargetInfo::getTargetDefines(const LangOptions &Opts, } if (HasZba) - Builder.defineMacro("__riscv_zba", "93000"); + Builder.defineMacro("__riscv_zba", "1000000"); if (HasZbb) - Builder.defineMacro("__riscv_zbb", "93000"); + Builder.defineMacro("__riscv_zbb", "1000000"); if (HasZbc) - Builder.defineMacro("__riscv_zbc", "93000"); + Builder.defineMacro("__riscv_zbc", "1000000"); if (HasZbe) Builder.defineMacro("__riscv_zbe", "93000"); @@ -206,7 +206,7 @@ void RISCVTargetInfo::getTargetDefines(const LangOptions &Opts, Builder.defineMacro("__riscv_zbr", "93000"); if (HasZbs) - Builder.defineMacro("__riscv_zbs", "93000"); + Builder.defineMacro("__riscv_zbs", "1000000"); if (HasZbt) Builder.defineMacro("__riscv_zbt", "93000"); diff --git a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp index aff96d80f765e..a05b8a93a37b0 100644 --- a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp +++ b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp @@ -58,9 +58,10 @@ static StringRef getExtensionType(StringRef Ext) { // extension that the compiler currently supports. static Optional<RISCVExtensionVersion> isExperimentalExtension(StringRef Ext) { - if (Ext == "zba" || Ext == "zbb" || Ext == "zbc" || Ext == "zbe" || - Ext == "zbf" || Ext == "zbm" || Ext == "zbp" || Ext == "zbr" || - Ext == "zbs" || Ext == "zbt") + if (Ext == "zba" || Ext == "zbb" || Ext == "zbc" || Ext == "zbs") + return RISCVExtensionVersion{"1", "0"}; + if (Ext == "zbe" || Ext == "zbf" || Ext == "zbm" || Ext == "zbp" || + Ext == "zbr" || Ext == "zbt") return RISCVExtensionVersion{"0", "93"}; if (Ext == "v" || Ext == "zvamo" || Ext == "zvlsseg") return RISCVExtensionVersion{"0", "10"}; diff --git a/clang/test/Driver/riscv-arch.c b/clang/test/Driver/riscv-arch.c index 269df87c2603f..e0afaa9e5351e 100644 --- a/clang/test/Driver/riscv-arch.c +++ b/clang/test/Driver/riscv-arch.c @@ -387,20 +387,20 @@ // RV32-EXPERIMENTAL-ZBB-NOFLAG: error: invalid arch name 'rv32izbb' // RV32-EXPERIMENTAL-ZBB-NOFLAG: requires '-menable-experimental-extensions' -// RUN: %clang -target riscv32-unknown-elf -march=rv32izbb0p93 -menable-experimental-extensions -### %s \ +// RUN: %clang -target riscv32-unknown-elf -march=rv32izbb1p0 -menable-experimental-extensions -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-ZBB %s // RV32-EXPERIMENTAL-ZBB: "-target-feature" "+experimental-zbb" -// RUN: %clang -target riscv32-unknown-elf -march=rv32izbb0p93_zbp0p93 -menable-experimental-extensions -### %s \ +// RUN: %clang -target riscv32-unknown-elf -march=rv32izbb1p0_zbp0p93 -menable-experimental-extensions -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-ZBB-ZBP %s // RV32-EXPERIMENTAL-ZBB-ZBP: "-target-feature" "+experimental-zbb" // RV32-EXPERIMENTAL-ZBB-ZBP: "-target-feature" "+experimental-zbp" -// RUN: %clang -target riscv32-unknown-elf -march=rv32izbb0p93zbp0p93 -menable-experimental-extensions -### %s \ +// RUN: %clang -target riscv32-unknown-elf -march=rv32izbb1p0zbp0p93 -menable-experimental-extensions -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-ZBB-ZBP-UNDERSCORE %s -// RV32-EXPERIMENTAL-ZBB-ZBP-UNDERSCORE: error: invalid arch name 'rv32izbb0p93zbp0p93', multi-character extensions must be separated by underscores +// RV32-EXPERIMENTAL-ZBB-ZBP-UNDERSCORE: error: invalid arch name 'rv32izbb1p0zbp0p93', multi-character extensions must be separated by underscores -// RUN: %clang -target riscv32-unknown-elf -march=rv32izba0p93 -menable-experimental-extensions -### %s \ +// RUN: %clang -target riscv32-unknown-elf -march=rv32izba1p0 -menable-experimental-extensions -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-ZBA %s // RV32-EXPERIMENTAL-ZBA: "-target-feature" "+experimental-zba" diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c index 2089a66a00754..a0a1ac59cc4cc 100644 --- a/clang/test/Preprocessor/riscv-target-features.c +++ b/clang/test/Preprocessor/riscv-target-features.c @@ -100,31 +100,31 @@ // CHECK-C-EXT: __riscv_compressed 1 // RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \ -// RUN: -march=rv32izba0p93 -x c -E -dM %s \ +// RUN: -march=rv32izba1p0 -x c -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-ZBA-EXT %s // RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \ -// RUN: -march=rv64izba0p93 -x c -E -dM %s \ +// RUN: -march=rv64izba1p0 -x c -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-ZBA-EXT %s // CHECK-ZBA-NOT: __riscv_b -// CHECK-ZBA-EXT: __riscv_zba 93000 +// CHECK-ZBA-EXT: __riscv_zba 1000000{{$}} // RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \ -// RUN: -march=rv32izbb0p93 -x c -E -dM %s \ +// RUN: -march=rv32izbb1p0 -x c -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-ZBB-EXT %s // RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \ -// RUN: -march=rv64izbb0p93 -x c -E -dM %s \ +// RUN: -march=rv64izbb1p0 -x c -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-ZBB-EXT %s // CHECK-ZBB-NOT: __riscv_b -// CHECK-ZBB-EXT: __riscv_zbb 93000 +// CHECK-ZBB-EXT: __riscv_zbb 1000000{{$}} // RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \ -// RUN: -march=rv32izbc0p93 -x c -E -dM %s \ +// RUN: -march=rv32izbc1p0 -x c -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-ZBC-EXT %s // RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \ -// RUN: -march=rv64izbc0p93 -x c -E -dM %s \ +// RUN: -march=rv64izbc1p0 -x c -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-ZBC-EXT %s // CHECK-ZBC-NOT: __riscv_b -// CHECK-ZBC-EXT: __riscv_zbc 93000 +// CHECK-ZBC-EXT: __riscv_zbc 1000000{{$}} // RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \ // RUN: -march=rv32izbe0p93 -x c -E -dM %s \ @@ -172,13 +172,13 @@ // CHECK-ZBR-EXT: __riscv_zbr 93000 // RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \ -// RUN: -march=rv32izbs0p93 -x c -E -dM %s \ +// RUN: -march=rv32izbs1p0 -x c -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-ZBS-EXT %s // RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \ -// RUN: -march=rv64izbs0p93 -x c -E -dM %s \ +// RUN: -march=rv64izbs1p0 -x c -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-ZBS-EXT %s // CHECK-ZBS-NOT: __riscv_b -// CHECK-ZBS-EXT: __riscv_zbs 93000 +// CHECK-ZBS-EXT: __riscv_zbs 1000000{{$}} // RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \ // RUN: -march=rv32izbt0p93 -x c -E -dM %s \ diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp index 7a73cdbbb1461..55c64d5669145 100644 --- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp +++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp @@ -2184,11 +2184,11 @@ bool RISCVAsmParser::parseDirectiveAttribute() { if (getFeatureBits(RISCV::FeatureStdExtZfh)) formalArchStr = (Twine(formalArchStr) + "_zfh0p1").str(); if (getFeatureBits(RISCV::FeatureStdExtZba)) - formalArchStr = (Twine(formalArchStr) + "_zba0p93").str(); + formalArchStr = (Twine(formalArchStr) + "_zba1p0").str(); if (getFeatureBits(RISCV::FeatureStdExtZbb)) - formalArchStr = (Twine(formalArchStr) + "_zbb0p93").str(); + formalArchStr = (Twine(formalArchStr) + "_zbb1p0").str(); if (getFeatureBits(RISCV::FeatureStdExtZbc)) - formalArchStr = (Twine(formalArchStr) + "_zbc0p93").str(); + formalArchStr = (Twine(formalArchStr) + "_zbc1p0").str(); if (getFeatureBits(RISCV::FeatureStdExtZbe)) formalArchStr = (Twine(formalArchStr) + "_zbe0p93").str(); if (getFeatureBits(RISCV::FeatureStdExtZbf)) @@ -2200,7 +2200,7 @@ bool RISCVAsmParser::parseDirectiveAttribute() { if (getFeatureBits(RISCV::FeatureStdExtZbr)) formalArchStr = (Twine(formalArchStr) + "_zbr0p93").str(); if (getFeatureBits(RISCV::FeatureStdExtZbs)) - formalArchStr = (Twine(formalArchStr) + "_zbs0p93").str(); + formalArchStr = (Twine(formalArchStr) + "_zbs1p0").str(); if (getFeatureBits(RISCV::FeatureStdExtZbt)) formalArchStr = (Twine(formalArchStr) + "_zbt0p93").str(); if (getFeatureBits(RISCV::FeatureStdExtZvamo)) diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp index 3a6245c861a30..8531f7bae5366 100644 --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp @@ -65,11 +65,11 @@ void RISCVTargetStreamer::emitTargetAttributes(const MCSubtargetInfo &STI) { if (STI.hasFeature(RISCV::FeatureStdExtZfh)) Arch += "_zfh0p1"; if (STI.hasFeature(RISCV::FeatureStdExtZba)) - Arch += "_zba0p93"; + Arch += "_zba1p0"; if (STI.hasFeature(RISCV::FeatureStdExtZbb)) - Arch += "_zbb0p93"; + Arch += "_zbb1p0"; if (STI.hasFeature(RISCV::FeatureStdExtZbc)) - Arch += "_zbc0p93"; + Arch += "_zbc1p0"; if (STI.hasFeature(RISCV::FeatureStdExtZbe)) Arch += "_zbe0p93"; if (STI.hasFeature(RISCV::FeatureStdExtZbf)) @@ -81,7 +81,7 @@ void RISCVTargetStreamer::emitTargetAttributes(const MCSubtargetInfo &STI) { if (STI.hasFeature(RISCV::FeatureStdExtZbr)) Arch += "_zbr0p93"; if (STI.hasFeature(RISCV::FeatureStdExtZbs)) - Arch += "_zbs0p93"; + Arch += "_zbs1p0"; if (STI.hasFeature(RISCV::FeatureStdExtZbt)) Arch += "_zbt0p93"; if (STI.hasFeature(RISCV::FeatureStdExtZvamo)) diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td index 0d686edc5d9fc..461bdd348934d 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td @@ -7,7 +7,17 @@ //===----------------------------------------------------------------------===// // // This file describes the RISC-V instructions from the standard Bitmanip -// extensions, version 0.93. +// extensions, versions: +// Zba - 1.0 +// Zbb - 1.0 +// Zbc - 1.0 +// Zbs - 1.0 +// Zbe - 0.93 +// Zbf - 0.93 +// Zbm - 0.93 +// Zbp - 0.93 +// Zbr - 0.93 +// Zbt - 0.93 // This version is still experimental as the Bitmanip extensions haven't been // ratified yet. // @@ -485,15 +495,6 @@ def RORW : ALUW_rr<0b0110000, 0b101, "rorw">, Sched<[WriteRotateReg32, ReadRotateReg32, ReadRotateReg32]>; } // Predicates = [HasStdExtZbbOrZbp, IsRV64] -let Predicates = [HasStdExtZbs, IsRV64] in { -// NOTE: These instructions have been removed from the 0.94 spec. As a result -// we have no isel patterns for them. -def BCLRW : ALUW_rr<0b0100100, 0b001, "bclrw">, Sched<[]>; -def BSETW : ALUW_rr<0b0010100, 0b001, "bsetw">, Sched<[]>; -def BINVW : ALUW_rr<0b0110100, 0b001, "binvw">, Sched<[]>; -def BEXTW : ALUW_rr<0b0100100, 0b101, "bextw">, Sched<[]>; -} // Predicates = [HasStdExtZbs, IsRV64] - let Predicates = [HasStdExtZbp, IsRV64] in { def GORCW : ALUW_rr<0b0010100, 0b101, "gorcw">, Sched<[]>; def GREVW : ALUW_rr<0b0110100, 0b101, "grevw">, Sched<[]>; @@ -507,17 +508,6 @@ let Predicates = [HasStdExtZbbOrZbp, IsRV64] in def RORIW : RVBShiftW_ri<0b0110000, 0b101, OPC_OP_IMM_32, "roriw">, Sched<[WriteRotateImm32, ReadRotateImm32]>; -let Predicates = [HasStdExtZbs, IsRV64] in { -// NOTE: These instructions have been removed from the 0.94 spec. As a result -// we have no isel patterns for them. -def BCLRIW : RVBShiftW_ri<0b0100100, 0b001, OPC_OP_IMM_32, "bclriw">, - Sched<[]>; -def BSETIW : RVBShiftW_ri<0b0010100, 0b001, OPC_OP_IMM_32, "bsetiw">, - Sched<[]>; -def BINVIW : RVBShiftW_ri<0b0110100, 0b001, OPC_OP_IMM_32, "binviw">, - Sched<[]>; -} // Predicates = [HasStdExtZbs, IsRV64] - let Predicates = [HasStdExtZbp, IsRV64] in { def GORCIW : RVBShiftW_ri<0b0010100, 0b101, OPC_OP_IMM_32, "gorciw">, Sched<[]>; def GREVIW : RVBShiftW_ri<0b0110100, 0b101, OPC_OP_IMM_32, "greviw">, Sched<[]>; @@ -615,8 +605,6 @@ def ORCB : RVInstI<0b101, OPC_OP_IMM, (outs GPR:$rd), (ins GPR:$rs1), //===----------------------------------------------------------------------===// let Predicates = [HasStdExtZba, IsRV64] in { -// NOTE: The 0.93 spec shows zext.w as an alias of pack/packw. It has been -// changed to add.uw in a draft after 0.94. def : InstAlias<"zext.w $rd, $rs", (ADDUW GPR:$rd, GPR:$rs, X0)>; } diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll index 7141fcd8b9edd..2be0535f678d5 100644 --- a/llvm/test/CodeGen/RISCV/attributes.ll +++ b/llvm/test/CodeGen/RISCV/attributes.ll @@ -44,17 +44,17 @@ ; RV32C: .attribute 5, "rv32i2p0_c2p0" ; RV32V: .attribute 5, "rv32i2p0_v0p10_zvamo0p10_zvlsseg0p10" ; RV32ZFH: .attribute 5, "rv32i2p0_f2p0_zfh0p1" -; RV32ZBA: .attribute 5, "rv32i2p0_zba0p93" -; RV32ZBB: .attribute 5, "rv32i2p0_zbb0p93" -; RV32ZBC: .attribute 5, "rv32i2p0_zbc0p93" +; RV32ZBA: .attribute 5, "rv32i2p0_zba1p0" +; RV32ZBB: .attribute 5, "rv32i2p0_zbb1p0" +; RV32ZBC: .attribute 5, "rv32i2p0_zbc1p0" ; RV32ZBE: .attribute 5, "rv32i2p0_zbe0p93" ; RV32ZBF: .attribute 5, "rv32i2p0_zbf0p93" ; RV32ZBM: .attribute 5, "rv32i2p0_zbm0p93" ; RV32ZBP: .attribute 5, "rv32i2p0_zbp0p93" ; RV32ZBR: .attribute 5, "rv32i2p0_zbr0p93" -; RV32ZBS: .attribute 5, "rv32i2p0_zbs0p93" +; RV32ZBS: .attribute 5, "rv32i2p0_zbs1p0" ; RV32ZBT: .attribute 5, "rv32i2p0_zbt0p93" -; RV32COMBINED: .attribute 5, "rv32i2p0_f2p0_v0p10_zfh0p1_zbb0p93_zvamo0p10_zvlsseg0p10" +; RV32COMBINED: .attribute 5, "rv32i2p0_f2p0_v0p10_zfh0p1_zbb1p0_zvamo0p10_zvlsseg0p10" ; RV64M: .attribute 5, "rv64i2p0_m2p0" ; RV64A: .attribute 5, "rv64i2p0_a2p0" @@ -62,18 +62,18 @@ ; RV64D: .attribute 5, "rv64i2p0_f2p0_d2p0" ; RV64C: .attribute 5, "rv64i2p0_c2p0" ; RV64ZFH: .attribute 5, "rv64i2p0_f2p0_zfh0p1" -; RV64ZBA: .attribute 5, "rv64i2p0_zba0p93" -; RV64ZBB: .attribute 5, "rv64i2p0_zbb0p93" -; RV64ZBC: .attribute 5, "rv64i2p0_zbc0p93" +; RV64ZBA: .attribute 5, "rv64i2p0_zba1p0" +; RV64ZBB: .attribute 5, "rv64i2p0_zbb1p0" +; RV64ZBC: .attribute 5, "rv64i2p0_zbc1p0" ; RV64ZBE: .attribute 5, "rv64i2p0_zbe0p93" ; RV64ZBF: .attribute 5, "rv64i2p0_zbf0p93" ; RV64ZBM: .attribute 5, "rv64i2p0_zbm0p93" ; RV64ZBP: .attribute 5, "rv64i2p0_zbp0p93" ; RV64ZBR: .attribute 5, "rv64i2p0_zbr0p93" -; RV64ZBS: .attribute 5, "rv64i2p0_zbs0p93" +; RV64ZBS: .attribute 5, "rv64i2p0_zbs1p0" ; RV64ZBT: .attribute 5, "rv64i2p0_zbt0p93" ; RV64V: .attribute 5, "rv64i2p0_v0p10_zvamo0p10_zvlsseg0p10" -; RV64COMBINED: .attribute 5, "rv64i2p0_f2p0_v0p10_zfh0p1_zbb0p93_zvamo0p10_zvlsseg0p10" +; RV64COMBINED: .attribute 5, "rv64i2p0_f2p0_v0p10_zfh0p1_zbb1p0_zvamo0p10_zvlsseg0p10" define i32 @addi(i32 %a) { diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s index 94a1f20054ffd..d2e756b19b6ea 100644 --- a/llvm/test/MC/RISCV/attribute-arch.s +++ b/llvm/test/MC/RISCV/attribute-arch.s @@ -40,13 +40,13 @@ # CHECK: attribute 5, "rv32i2p0_v0p10" .attribute arch, "rv32izba" -# CHECK: attribute 5, "rv32i2p0_zba0p93" +# CHECK: attribute 5, "rv32i2p0_zba1p0" .attribute arch, "rv32izbb" -# CHECK: attribute 5, "rv32i2p0_zbb0p93" +# CHECK: attribute 5, "rv32i2p0_zbb1p0" .attribute arch, "rv32izbc" -# CHECK: attribute 5, "rv32i2p0_zbc0p93" +# CHECK: attribute 5, "rv32i2p0_zbc1p0" .attribute arch, "rv32izbe" # CHECK: attribute 5, "rv32i2p0_zbe0p93" @@ -64,7 +64,7 @@ # CHECK: attribute 5, "rv32i2p0_zbr0p93" .attribute arch, "rv32izbs" -# CHECK: attribute 5, "rv32i2p0_zbs0p93" +# CHECK: attribute 5, "rv32i2p0_zbs1p0" .attribute arch, "rv32izbt" # CHECK: attribute 5, "rv32i2p0_zbt0p93" _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
