khchen created this revision. khchen added reviewers: craig.topper, rogfer01, frasercrmck, kito-cheng, arcbbb, monkchiang, eopXD. Herald added subscribers: VincentWu, luke957, achieveartificialintelligence, vkmr, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, edward-jones, zzheng, jrtc27, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, hiraditya. khchen requested review of this revision. Herald added subscribers: llvm-commits, cfe-commits, pcwang-thead, MaskRay. Herald added projects: clang, LLVM.
The goal is support tail and mask policy in RVV builtins. We focus on IR part first. The nomask vector Multiply-Add need a policy operand because merge value could not be undef. Repository: rG LLVM Github Monorepo https://reviews.llvm.org/D119727 Files: clang/include/clang/Basic/riscv_vector.td clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmacc.c clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmadd.c clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmsac.c clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmsub.c clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmacc.c clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmadd.c clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmsac.c clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmsub.c clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwmacc.c clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwmsac.c clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwnmacc.c clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwnmsac.c clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmacc.c clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmadd.c clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnmsac.c clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnmsub.c clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwmacc.c clang/test/CodeGen/RISCV/rvv-intrinsics/vfmacc.c clang/test/CodeGen/RISCV/rvv-intrinsics/vfmadd.c clang/test/CodeGen/RISCV/rvv-intrinsics/vfmsac.c clang/test/CodeGen/RISCV/rvv-intrinsics/vfmsub.c clang/test/CodeGen/RISCV/rvv-intrinsics/vfnmacc.c clang/test/CodeGen/RISCV/rvv-intrinsics/vfnmadd.c clang/test/CodeGen/RISCV/rvv-intrinsics/vfnmsac.c clang/test/CodeGen/RISCV/rvv-intrinsics/vfnmsub.c clang/test/CodeGen/RISCV/rvv-intrinsics/vfwmacc.c clang/test/CodeGen/RISCV/rvv-intrinsics/vfwmsac.c clang/test/CodeGen/RISCV/rvv-intrinsics/vfwnmacc.c clang/test/CodeGen/RISCV/rvv-intrinsics/vfwnmsac.c clang/test/CodeGen/RISCV/rvv-intrinsics/vmacc.c clang/test/CodeGen/RISCV/rvv-intrinsics/vmadd.c clang/test/CodeGen/RISCV/rvv-intrinsics/vnmsac.c clang/test/CodeGen/RISCV/rvv-intrinsics/vnmsub.c clang/test/CodeGen/RISCV/rvv-intrinsics/vwmacc.c clang/utils/TableGen/RISCVVEmitter.cpp llvm/include/llvm/IR/IntrinsicsRISCV.td llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td llvm/test/CodeGen/RISCV/rvv/memory-args.ll llvm/test/CodeGen/RISCV/rvv/unmasked-ta.ll llvm/test/CodeGen/RISCV/rvv/vfmacc.ll llvm/test/CodeGen/RISCV/rvv/vfmadd.ll llvm/test/CodeGen/RISCV/rvv/vfmsac.ll llvm/test/CodeGen/RISCV/rvv/vfmsub.ll llvm/test/CodeGen/RISCV/rvv/vfnmacc.ll llvm/test/CodeGen/RISCV/rvv/vfnmadd.ll llvm/test/CodeGen/RISCV/rvv/vfnmsac.ll llvm/test/CodeGen/RISCV/rvv/vfnmsub.ll llvm/test/CodeGen/RISCV/rvv/vfwmacc.ll llvm/test/CodeGen/RISCV/rvv/vfwmsac.ll llvm/test/CodeGen/RISCV/rvv/vfwnmacc.ll llvm/test/CodeGen/RISCV/rvv/vfwnmsac.ll llvm/test/CodeGen/RISCV/rvv/vmacc-rv32.ll llvm/test/CodeGen/RISCV/rvv/vmacc-rv64.ll llvm/test/CodeGen/RISCV/rvv/vmadd-rv32.ll llvm/test/CodeGen/RISCV/rvv/vmadd-rv64.ll llvm/test/CodeGen/RISCV/rvv/vnmsac-rv32.ll llvm/test/CodeGen/RISCV/rvv/vnmsac-rv64.ll llvm/test/CodeGen/RISCV/rvv/vnmsub-rv32.ll llvm/test/CodeGen/RISCV/rvv/vnmsub-rv64.ll llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll llvm/test/CodeGen/RISCV/rvv/vwmacc-rv32.ll llvm/test/CodeGen/RISCV/rvv/vwmacc-rv64.ll llvm/test/CodeGen/RISCV/rvv/vwmaccsu-rv32.ll llvm/test/CodeGen/RISCV/rvv/vwmaccsu-rv64.ll llvm/test/CodeGen/RISCV/rvv/vwmaccu-rv32.ll llvm/test/CodeGen/RISCV/rvv/vwmaccu-rv64.ll llvm/test/CodeGen/RISCV/rvv/vwmaccus-rv32.ll llvm/test/CodeGen/RISCV/rvv/vwmaccus-rv64.ll _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits